PSoC™ 5, 3 & 1 Forum Discussions

 Hello everyboby,

I'm trying to use voltage follower in my system. But I find that no matter what input signal inputs to voltage follower, only positive part can be output from voltage follower.  I'm confusing that if I set the voltage follower in wrong way or if there are some other setting of the board. 

Here is the detail of my experiment:

I just used a voltage follower whose input+ is port 0[2] and output is port 0[1].

I also set the power of voltage follower to 'High power'.

In my code, I add 'Opamp_1_Start();' into for loop. 

the input signal is sine wave with 1kHz, 1 Vpp and 0 offset. 

But the output of voltage follower only have the positive-value part shown in attached picture. 

I really want to know what's wrong with it? Thank you so much!

there are always warning as follows  during the reinstallation of designer 5.4.

//

the wizard was interrupted before PSoC Designer could be completely installed.

Your system has not beed\n modified. To install this program at a later time,please run the setup again.

//

I have tried many times to attempt to reinstall the program. How to solve the problem? Thanks o a lot!

Hello All,

I am an absolute newbie to SPI and using it with these PSoCs.

I have not found adequate documentation or examples on how to perform SPI Master READ.

I am able to write data to the SPI slave device, however how do you read data?

Using Oscilloscope, I can see that the SCLK pin is driven during a write operation, but it is not being driven during a read command!!! (It remains low)

I call:

SPIM_WriteTxData(0x80);

while((SPIM_ReadTxStatus()&8)==0);

SPIM_WriteTxData(0x10);

while((SPIM_ReadTxStatus()&8)==0);

SPIM_TxDisable();
        
PSOC_DEBUG_BUF[15] = SPIM_ReadRxData();

I can see SCLK and SDIO is driven during the two write cycles, and the correct bits are set, however SCLK is never driven for the SPI Slave Device to write data!!

How is SCLK driven for read mode?

-Thank you!

-Gytis

 hello, I'm a beginner to psoc1. when i building codes in psoc designer5.4, there always are several errors,which can be built in other's PC successfully.

errors are as follows:

 hello, I'm a beginner to psoc1. when i building codes in psoc designer5.4, there always are several errors,which can be built in other's PC successfully.

errors are as follows:

 i am  transfering data from hyperterminal to psoc and writing it  on external eeprom but not working attaching the code. pls suggest.

Hi.

Im looking at the feasibility of using a PSoC 3 device for a project of mine. I need to be able to communicate with a USB Webcam (USB Device). So can I configure the USB in the PSoC3 device to function as a USB Host? All the application notes have used the USB in the PSoC3 as a usb device. So is the host controller not part of the PSoC3 package?

If the USB cannot function as a host, can you suggest some alternatives? Is there a way I can work around this and still use the PSoC3?

Also, are there any PSoCs available which support high speed USB?

Thanks in advance.

Regards,

Karthik

I have a question regarding PLD power draw, particularly digital blocks with a very slow (or no) clock.
I have an application I'm considering porting to PSOC, but before I do I'd like to hear what the consensus is about running PLD blocks in very low power designs.     

The design needs to sleep for the majority of its lifetime as it is battery powered, and must last several years. the device wakes up roughly once every second for about 1ms, and should have an average power draw below 40uA.     

I now want to extend the device to incorporate a receiver for a very low data-rate serial protocol. essentially the receiver device will send a wake signal to its micro, followed by a clocked data stream of about 2ms per bit (500 baud). Capturing the data is very easy. In my current micro implementation I sample the data with an interrupt triggered by the clock line. The problem with this is power. As it is currently I have to keep my micro awake for the entire duration of the data transfer (~100ms), which basically kills any aspirations I have for a lower power device.     

I thought the project might be a good candidate for a PSoC, as I could use an SPI block or even a custom Verilog based block to capture the data, and wake my micro a fixed timeout period after the data has stopped.     

My question is, will a psoc PLD block draw little enough current if it has a very slow (just the 2ms data clock line, perhaps a 32khz source for timeout...). Can I even have PLD blocks running in sleep modes? Would it be more effective to have the micro simply wake briefly every time the clock line activates?