PSoC™ 5, 3 & 1 Forum Discussions
Hi,
My requirement is to output data in microseconds, and I am using many timer interrupts to achieve it in my code. The result is unexpected jitters in the o/p. It's definately not a good approach to have implementation inside ISR's, however i cannot think of anything else to achieve this timing. Any suggestions ??
Note : The max tolerance allowed in the system is 2us. (Simple function execution take 1us)
HW : PSOC5LP, Creator 3.0
Screenshot : 5 timers are being used, Timer_Period_0 works fine, but Timer_Period_1 has varying intervals of 496, 504, 496, 504. I am not able to understand this behavior. Any help will be highly appreciated.
Show LessI found following code in forums
It's a code for filtering process
can any body explaing any line of this code?
I want to give input from psoc5lp's input pin to DFB but I think in this code inputs are fixed in data ramA
I attached the code
Show LessThe PSoC 3 CY8C38 Family Datasheet says:
- Simultaneous access of SRAM by the 8051 and the DMA controller is possible if different 4-KB blocks are accessed.
It also says in PHUB Features:
- Simultaneous CPU and DMA access to peripherals located on different spokes
I notice though that it only lists one PHUB Spoke (0) for SRAM.
What I'd been wondering, if I have a Group 1 UDB on Spoke 6, and a Group 2 UDB on Spoke 7, would they be able to DMA concurrently to different 4KB SRAM blocks?
thanks
A.
I have a project that needs to output a 125 kHz signal, modulated by 2400 Baud data stream.
Before I reort to bit-bashing the application, I thought I would see if there might be a simpler way to do this uing internal components.
The physical output needs to have the 125 kHz ASK modulated waveform appearing in in a push-pull fashion on 2 pins (one pin is high whiel other is low. This is ok, I can use a NOT gate for second pin.
When the system is not sending data, I need an ENABLE output.
I was hoping I could have an enable function internally that set a 125 kHz generator of some sort running (clock/PWM ?)
as well as the enable signal appearing on a digital output. The generator output would appear at 2 pins when enabled and producce hi/low transitions at 125 kHz (one pin will produce high/low and other low/high).
Then some way of applying a stream of Data (2400 Baud) to modulate the generator on and off.
Any ideas much appreciated
thsnks
Show LessI "m using Psoc1 CY8C28452 device . Everything complied level as long as used digital blocks. But when use any analog user module and write to compile with any one instruction from its datasheet I get a message that "undefined function". Can anybody help?
Show LessI am working with PSOC 3, and I am using internal EEprom block that I can scan serial number to.
What I would like to achieve is that when I down load a hex file via PSOC programmer, I would like to get prompted to scan a serial number. Does any one have an idea?
Thanks!
Show LessI found following code in forums
It's a code for filtering process
can any bode explaing any line of this code?
I want to give input from psoc5lp's input pin to DFB but I think in this code inputs are fixed in data ramA
I attached the code
Show LessI have an unusual problem with reading the correct value from the CyResetStatus variable. I start the watchdog and then delay much longer than the alloted time. My system resets and I place a breakpoint on the first line in 'main'. I have a bootloader timeout of 2 seconds, which I assume is called but then resets the micro after the timeout is exceeded and places the program counter back to the application where my breakpoint is at.
I have read several docs that point me to using this variable, but the reset status variable always returns 0xA0? The top most bit is being set in the bootloader I think, but the watchdog timeout bit is never being set. Any ideas?
Thanks
Show LessI'm working on a project where I'd like to have a counter increment with a base other than 1, i.e.:
A = A+Base
So far I've used a PulseConverter and TFF to convert the single pulse to Base pulses into a Counter UDB component, which sort of works, but of course takes Base clock cycles to increment.
Any better solutions?
I'm currently looking at the UDB Editor to see if I can make one there directly.
thanks,
A.
Show Less