PSoC™ 5, 3 & 1 Forum Discussions
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Hi
I use application AN2284 to create notch filter 50Hz. In this app is C code
IIR second-order notch filter:
diff1 = (x + xn_2) <<16;
y = ((diff1>>1)+(diff1>>2)+87301*(xn_1 - yn_1) -((yn_2<<16)>>1));
xn_2 = xn_1;
xn_1 = x;
yn_2 = yn_1;
yn_1 = y;
I know IIR filters but I don't understand where it came from value 87301 ?
I thought that the filter is formed from the coefficients. for example. b=-2*cos(2*PI*f)
I would be grateful someone explain how it works.
Show LessI'm using PSOC Creator 2.2, SPI_Slave_v2_50, targeting a CY8C5868AXI-LP032.
I can't seem to get the SPI slave to work at all. I have confirmed all three incoming signals from a different processor, these signals being ss, sclk, and mosi. So I know that those signals are getting inside the PSOC, with a clock rate of roughly 96kHz. However, I can't seem to get any response out of the SPI slave component, as measured on the rx_interrupt output in multiple ways.
I've attached images of my TopDesign and the three configuration tabs for the SPI slave. I've also pasted the relevant source code below, taken largely from the Cypress example. The entry point is init_spis_psoc() near the bottom.
In the recent past, I routed each of the three incoming signals (ss, sclk, mosi) directly to one of my LED output pins. I confirmed with a scope that the LED was blinking exactly as the measured SPI signal being generated by a different processor. However, I don't see the result from the dma. I don't see an interrupt happening, whether it was at the moment configured to blink an LED or if I set a breakproint with the debugger. I made sure to call my ISR from inside the automatically generated ...ISR.c files And most recently I don't see an LED output in response to interrupts occurring, having routed the interrupt outputs directly to my LED pins. I've tentatively enabled all external interrupt types. I've set the bit rate to 1000 kHz, ten times faster than the actual sclk, and I've set to internal clock to be sure. The SPI slave just seems totally dead.
What am I possibly doing wrong?
#ifdef DO_SPIS_PSOC
/* DMA Configuration for DMA_TX_S */
#define DMA_TX_S_BYTES_PER_BURST (1u)
#define DMA_TX_S_REQUEST_PER_BURST (1u)
#define DMA_TX_S_SRC_BASE (CYDEV_SRAM_BASE)
#define DMA_TX_S_DST_BASE (CYDEV_PERIPH_BASE)
/* DMA Configuration for DMA_RX_S */
#define DMA_RX_S_BYTES_PER_BURST (1u)
#define DMA_RX_S_REQUEST_PER_BURST (1u)
#define DMA_RX_S_SRC_BASE (CYDEV_PERIPH_BASE)
#define DMA_RX_S_DST_BASE (CYDEV_SRAM_BASE)
/* Variable declarations for DMA_Tx_S */
uint8 S_TxChannel;
uint8 S_TxTD[2u];
/* Variable declarations for DMA_Rx_S */
uint8 S_RxChannel;
uint8 S_RxTD[2u];
#define TX_TD_SIZE 128
#define RX_TD_SIZE 128
uint8 s_txBuffer[TX_TD_SIZE];
uint8 s_rxBuffer[RX_TD_SIZE];
/*******************************************************************************
* Function Name: Dma_M_Tx_Configuration
********************************************************************************
* Summary:
* Configures the DMA transfer for TX direction
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void Dma_S_Tx_Configuration()
{
cystatus status;
/* Init DMA, 1 byte bursts, each burst requires a request */
S_TxChannel = DMA_TX_S_DmaInitialize(DMA_TX_S_BYTES_PER_BURST, DMA_TX_S_REQUEST_PER_BURST,
HI16(DMA_TX_S_SRC_BASE), HI16(DMA_TX_S_DST_BASE));
S_TxTD[0u] = CyDmaTdAllocate();
S_TxTD[1u] = CyDmaTdAllocate();
/* Configure this Td chain as follows:
* - The TD is looping on itself
* - Increment the source address, but not the destination address
*/
status = CyDmaTdSetConfiguration(S_TxTD[0u], 7u, S_TxTD[1u], TD_INC_SRC_ADR);
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Tx_Configuration;
status = CyDmaTdSetConfiguration(S_TxTD[1u], 1u, S_TxTD[1u], 0u);
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Tx_Configuration;
/* From the memory to the SPIS */
#if(CY_PSOC3_ES2 || CY_PSOC5_ES1)
status = CyDmaTdSetAddress(S_TxTD[0u], LO16((uint32)s_txBuffer), LO16((uint32)SPIS_PSOC_BSPIS_es2_SPISlave_sR8_DpMISO_u0__F0_REG));
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Tx_Configuration;
#else
status = CyDmaTdSetAddress(S_TxTD[0u], LO16((uint32)s_txBuffer), LO16((uint32)SPIS_PSOC_BSPIS_es3_SPISlave_sR8_Dp_u0__F0_REG));
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Tx_Configuration;
#endif
status = CyDmaTdSetAddress(S_TxTD[1u], LO16((uint32)s_txBuffer), LO16((uint32)s_txBuffer));
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Tx_Configuration;
/* Associate the TD with the channel */
status = CyDmaChSetInitialTd(S_TxChannel, S_TxTD[0u]);
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Tx_Configuration;
return;
FAIL_Dma_S_Tx_Configuration:
UART_UPSTRM_PutString("SPIS_PSOC Dma_S_Tx_Configuration FAILED\r\n");
}
/*******************************************************************************
* Function Name: Dma_S_Rx_Configuration
********************************************************************************
* Summary:
* Configures the DMA transfer for RX direction
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void Dma_S_Rx_Configuration()
{
cystatus status;
/* Init DMA, 1 byte bursts, each burst requires a request */
S_RxChannel = DMA_RX_S_DmaInitialize(DMA_RX_S_BYTES_PER_BURST, DMA_RX_S_REQUEST_PER_BURST,
HI16(DMA_RX_S_SRC_BASE), HI16(DMA_RX_S_DST_BASE));
S_RxTD[0u] = CyDmaTdAllocate();
S_RxTD[1u] = CyDmaTdAllocate();
/* Configure this Td as follows:
* - The TD is looping on itself
* - Increment the destination address, but not the source address
*/
status = CyDmaTdSetConfiguration(S_RxTD[0u], 8u, S_RxTD[1u], TD_INC_DST_ADR);
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Rx_Configuration;
status = CyDmaTdSetConfiguration(S_RxTD[1u], 1u, S_RxTD[1u], 0u);
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Rx_Configuration;
/* From the SPIS to the memory */
#if(CY_PSOC3_ES2 || CY_PSOC5_ES1)
status = CyDmaTdSetAddress(S_RxTD[0u], LO16((uint32)SPIS_PSOC_BSPIS_es2_SPISlave_sR8_DpMOSI_u0__F0_REG), LO16((uint32)s_rxBuffer));
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Rx_Configuration;
#else
status = CyDmaTdSetAddress(S_RxTD[0u], LO16((uint32)SPIS_PSOC_BSPIS_es3_SPISlave_sR8_Dp_u0__F1_REG), LO16((uint32)s_rxBuffer));
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Rx_Configuration;
#endif
status = CyDmaTdSetAddress(S_RxTD[1u], LO16((uint32)s_rxBuffer), LO16((uint32)s_rxBuffer));
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Rx_Configuration;
/* Associate the TD with the channel */
status = CyDmaChSetInitialTd(S_RxChannel, S_RxTD[0u]);
if (CYRET_SUCCESS != status) goto FAIL_Dma_S_Rx_Configuration;
return;
FAIL_Dma_S_Rx_Configuration:
UART_UPSTRM_PutString("SPIS_PSOC Dma_S_Rx_Configuration FAILED\r\n");
}
void SPIS_PSOC_RX_ISR(void)
{
ToggleDebugA(); // Toggle RED LED
SPIS_PSOC_RX_ISR_ClearPending();
}
void SPIS_PSOC_TX_ISR(void)
{
ToggleDebugA(); // Toggle RED LED
SPIS_PSOC_TX_ISR_ClearPending();
}
void init_spis_psoc()
{
PSOC_SPI_MISO_PIN_SetDriveMode(PSOC_SPI_MISO_PIN_DM_STRONG); // Make strong output
PSOC_SPI_MOSI_PIN_SetDriveMode(PSOC_SPI_MOSI_PIN_DM_DIG_HIZ);
PSOC_SPI_CLK_SetDriveMode(PSOC_SPI_CLK_DM_DIG_HIZ);
nCS_PSOC_PIN_SetDriveMode(nCS_PSOC_PIN_DM_DIG_HIZ);
SPIS_PSOC_RX_ISR_Start();
SPIS_PSOC_TX_ISR_Start();
Dma_S_Tx_Configuration();
Dma_S_Rx_Configuration();
CyDmaChEnable(S_TxChannel, 1u);
CyDmaChEnable(S_RxChannel, 1u);
SPIS_PSOC_Start();
UART_UPSTRM_PutString("SPIS_PSOC initialized\r\n");
}
#endif
Hi Dana
I try to use usbfs_audio example project
I didn't hear any voice in my speaker (I try the speaker in another project and the speaker works well)
I use a speaker with 8 ohm impadence and psoc 3.0 creator
How can I make it work?
second question: what is the best option to stream audio file from computer to Psoc -5 and to back to pc?
Thanks
Show LessHello everyone,
I am new to capsense. I have CY8C20637-24LQXI and I am trying to dump hex file into it using MiniProg 1. However I am facing issue in same. I am getting protect failed error. I think there is no issue with connection as I can successfully update firmware. Log of process is same as below..
Programming Terminated
===> Protect Failed
Doing Protect
Program & Verify Succeeded
Program & Verify Starting
Erase Succeeded
Silicon: 0149, Family/Die: 55, Major Rev: A
Program Requested at 6:50:21 PM
Please provide me with some inputs or suggestions so I can overcome this issue.
Thanks,
Sujit
Show LessHello everyone,
We've implemented our real-time application using CY8CKIT-050 PSoC®5 Development Kit. Now we are trying to design our own board. An on-board programming interface with pc through a usb connector is required to write program to the PSoC5 chip. But we don't know how to design this part.
Up to now, I found two ways to make it possible. One is FX2LP programmer circuitry from Kit-050. Another one is MiniProg3 which is kind of expensive for us. We are wondering if there are other methods to implement an On-board Programming Interface. Thank you so much !
Best Regards,
Show LessIs there a production programmer available for programming PSCO 4 ? (28 pin SOIC package).
Or do we need to get our own ZIF socket and roll a PCB with the socket and interface to the SWD pins for programming?
I do not require high volume, I simply want to avoid having to provide connector for programming on the target once installed into product.
I was thinking maybe a 28 pin SOIC ZIF socket on a board with 3V regulator and 10 pin Box header to suit the Miniprog 3 and use Creator to program the ICs before I solder them onto the target PCB.
Thanks
Show LessHi
I build ECG on CY8C27443 its working fine. But sometimes when I touch (knock) electrodes resets the processor. Program starts again. Attached schematic.
Please help
Show LessHi,
I did some work on a circuit board to convert a load cell output (0-15mV) into a force that is transmitted to a PC. The software worked fine, and then I lost it, and recreated it. Now nothing seems to work. There are a few things that stick out:
-The load ADC does not read accurately at all, and bounces around a lot. If I set it up as it is in the file, it reads off when given a 10mV signal. It reads off about 40%, and bounces around. If I set it up as a level shift buffer in order to maximize the resolution it actually reads negative.
-There is an error by my first interrupt handler that I do not understand.
-A lot of the 'smart completion' selections are missing entirely. I try to type 'UART_PutString' and it never appears under the smart completion options.
Any ideas are greatly appreciated.
Thank you,
Tom
Show LessAfter experiencing Hard Resets due to EMI from an adjacent unit, I came to the realization that EMI Resets were going to be a difficult to eliminate. The CY8CKIT-030 was used for a development test bench; I hardly expected to do a better job of PCB design than Cypress engineers. And I would not be able to control the environment that the embedded PSoC3 would be installed in.
This thread focuses on trying to figure out how to "peacefully" co-exist with Resets, both Soft and Hard varieties.
Since there are two varieties of Resets, the first item is to determine the type currently occurring.
Resets of the Soft variety are easier to work with; they leave SRAM as is and the Components and Registers are not reset to DWR settings. User code is resumed at main(). The main Soft Reset is the WDT Reset. RESET_SR0 contains the identity since the Registers are not reset. But lacking in support is a means to determine where in your code the WDT tripped, and a count of how many have occurred. Because the Stack has no meaning, and the Soft Reset clears the CPU registers, "crawling" the Stack (if idata was left uncleared) could possibly answer where the WDT tripped. A count of WDT events could be a user responsibility; SRAM as a count repository is possible (but an intervening Hard Reset clears SRAM and the WDT count would be lost). The normal main() function of initializing Components should probably be skipped with a Soft Reset. If the problem section of code can be determined, then selective initialization may cure the WDT problem.
Hard Resets pose a significant challenge. The action to be taken is highly dependent on the functions that the PSoC3 is designed to make.
With SRAM clearing as an option on a startup reset, the tradeoff of fast startup versus using a Global Variable as an SRAM clearing semaphore should be evaluated. Yes, CyResetStatus could be used to see what type of Hard Reset occurred (I have done extensive research of CyResetStatus and conclude it is not currently working for PSoC3 with Creator 3.0 SP2). But if the reset is of the PRESx variety then a working CyResetStatus does not set a bit (I experienced bad enough EMI to cause a PRESx set with LVID and LVIA not activated).
The Hard reset SRAM semaphore works by declaring a Global Variable that is not initialized. The last thing main() does is set the variable to a one. On entry to main(), examination of the variable shows if SRAM was cleared and thus a Hard Reset has occurred. A POR or XRES will show a zero semaphore. If the semaphore still contains the one, a Soft reset occurred (assumes that SRAM Clear remains the option).
How to handle a Hard reset is the main consideration. I will explore what I am considering in followup posts. I am not sure with my particular project how to handle Hard resets. This thread is to solicit comments and suggestions which are welcomed.
Thanks for your interest,
Bruce
Show Less