PSoC™ 5, 3 & 1 Forum Discussions
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Hello folks,
My device will be self-powered and thus will require VBus monitoring as discussed in the USB datasheet under ComponentParameters/AdvancedTab/EnableVBusMonitoring.
I understand the requirment.
What I am unsure of is the difference between the Internal and External VBus options. Both provide a pin to connect to (the host suppllied) VBus. The External option requires you to hook up that pin manually within the schematic.
Do they both require the resistor/cap network as shown in the diagram in the datasheet or is it just the External option? If they do then I don't understand why the two options exist.
Can someone give me a brief explanation as to the difference between the options?
Thanks,
Stephen
I need to create a bootloader using a CAN bus component. I've read the bootloader component datasheet as well as AN73854, AN73503, and AN68272 but I'm still a bit confused. In the attached project I have a bootload component and a CAN component. The CAN component is not listed as an option under the "Communication component" in the bootloader setup dialog so I'm going with "Custom Interface". This means I have to define 5 different API function (i.e. - Start, Stop, Reset, Write, and Read). This is where I start getting confused. I'd like for the interface to be compatible with PC side (host) software tools that we already have for our current microprocessors. That is, we have a protocol defined already for things like "ENTER BOOTLOAD MODE" and "WRITE FLASH ADDRESS". I'm confused enough to not even know what to exactly ask here. Just any help to get me going would be much appreciated!
Show LessHey everybody,
I'm using the ARM CMSIS DSP libraries, one of the functions I'm using is arm_cfft_q15.
This file keeps triggering an error though:
Build error: undefined reference to `arm_bitreversal_16'.
The function that it is referring to is an assembly function found in the file arm_bitreversal2.s and I have made sure that file is in the source file.
I noticed that none of the header files from the CMSIS files reference this assembly file, and as far as I can tell I have included all the proper headers and source files in the project and I have followed the method shown here to set up the CMSIS libraries with the project: http://www.cypress.com/knowledge-base-article/including-cortex-microcontroller-software-interface-standard-cmsis-library.
any suggestions or help would be very appreciated, I attached my project in case anyone wanted to see it.
Thanks in advance,
scarlson
Show LessHello Friends I have a problem whith RX interrupt, I only want to read when I have a data, but the interruption comes once and then, never comes to interrupt again, I attach my code
Show LessI'm using the control regsister "DmaMsbReg" as the destination of a DMA transfer. My custom component (MyOverlay) uses the value of this register on lines 251, 253 and 255 of MyOverlay.v. However, the register is being removed from cyfitter.h. Why? It appears in cyfitter.h as the following:
/* DmaMsbReg */
#define DmaMsbReg_Sync_ctrl_reg__REMOVED 1u
Show LessHi,
I am facing the following problem:
I want to create boot loader and bootloadable project. But i am not seeing the advance settings in creator 3.2. How i can do this?
I attached the pic for better understanding of my problem.
Looking forward for your replies.
Regards
Awais
Show LessHello,
I have already read "Getting started with CapSense" and the "PSoC3 and PSoC5LP CapSense Design Guide" but I still have a question regarding how CapSense works. In the design guide you will find figure 2-3 CapSense CSD Block Diagramm. For example I start scanning whether Button1 is pressed or not. CMOD is charged via SW3 and the source current. If the voltage equals a reference, the sigma delta converter opens SW3. The converter counts the ticks, how long SW3 is closed. From the amount of ticks you can say if the button is pressed or not.
What I don't understand is SW2 and SW1. I started the scanning and SW3 is open since CMOD is charged. Then SW1 and SW2 are opening and closing alternatively. Lets say the button is pressed and SW1 is closed and so SW2 is open. Cx is discharging CMOD depending on the capacitance of Cx. Then SW1 and SW2 change states so Cx is being discharged. And this will repeat several times.
Is CMOD charged completely again in one cycle, so if SW1 closes again, SW3 will be open or can it happen, that when SW1 is closed, SW3 is closed as well?
Best regards.
Show LessI'm sure there's a forum post about this already. However, whenever I Google this the links always take me to the cypress homepage, rather than the forum post.
I'm using the CY8CKIT-042-BLE and PSOC 3.1. When I go to select debug target, I'm greeted with "Port Aqcuire Failed". I have checked the cable and closed any application that may use the port.
Show LessTaking some old discrete circuits and embedding them into a PSoC 5LP CY8CKIT-059. Came across this one when using the WaveDAC component. It appears the output frequency is one half the set frequency in PSoC Creator. Is this a known bug or something simple I have overlooked?
Appreciate any feedback.
Show LessNice to meet you.
I am troubled now unexpected CPU reset.
Frequency with which it occurs is about once per hour.
It uses the watchdog timer,but is it not the cause.
In the main routine just to be sure, I'm writing to...
main()
{
CyVdLvDigitDisable();
CyVdLvAnalogDisable();
CyVdHvAnalogDisable();
It is quite troubled, but there is no place to come to mind in the other.
I think there are cases where the same thing is happening in other user?
Type name of the CPU,CY8C5868AXI-LP035(PSOC5LP).
Development envrionment PSoC Creator 2.2 SP1
Use external clock 24MHz OSC-IC.
Show Less