PSoC™ 5, 3 & 1 Forum Discussions
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Hi,
Using a PGA to buffer a small signal before input to a mux and ATD. The part is configured to use Internal Vss.
In the program, I accidently forgot to turn it on via PGA_Start() yet it does give me a directly proportional output with a range that is repeatable and can be calibrated. If the part is turned on, then the dynamic range is reduced to an unusable range, though the ATD count is much higher.
Is the part actually in a low power state and receiving power if I fail to do a PGA_Start()?
Show LessHi all,
I'm making a easy project, but i haven't the results i'm expecting. In few days i will use a analog transducer, it give me back a voltage, around 100mV peak to peak, so i'm trying to 'simulate' it with the WaveDac component (generating a 0.5 volts sine wave), attached to a ADC_DeltaSigma configured to 16 bits, continuous mode, 16 bits.
The convertion is sent via UART to my pc, i'm expecting a voltage from 0.250 v - 0.750, all i get is 0.350 and 0.650 results printed on the terminal.
Any suggestions on this topic? It seems like i'm getting a 300 mV sine wave, i already try it with the buffered output on the WaveDac component with no improvements.
Find attached my project.
Carlos
Show LessI come from programming applications and webpages using C# to helping with a psoc project. So in c# and such if needed i could create controls from code behind on the fly as needed.
Im looking to see if that is possible with PSoC 5LP dev kit or possible in PSoC at all.
We are working on a project that requires the other programmer to only use or my logic as he doesnt have much room / space within the memory we are using on the board or whatever, not sure as im not a PSoC person.
Im trying to help and got everything working, just need to see if i can accomplish the same thing in code only
Show LessHi,
we have a timing sensitive design (part of it), that is hand optimized for max performance (highest possible clock) to meet the setup and hold timings. Most other parts do have much lower requirements. It seems that cydsfit will optimize all parts with the same rules.
Is there a way to define a timing constraint for some signals or clock domains, that will become a much higher priority while routing over others?
We also designed the project with Creator 3.0. After updating to 3.3 the timing results a much lower. Therefore we had to switch back, because the design is tested and in production.
Kindly regards,
Franz
Show LessHello Community,
Before I make the experiment, maybe somebody already has an idea about this.
I'm designing an board where a PSOC5LP will be the power monitor/controller and it will also control some of the onboard ICs through SPI I2C etc etc.
Some of those ICs will be a on a power domain that can collapse or just be disabled by the PSOC it self (with all the precautions of this scenario), which will also collapse one of the VDDIO domains, where the ICs will interface the PSOC.
Will this affect proper operation on the rest of the chip? Will the PSOC power domain be robust to such scenario? I'm wandering if some ESD protection will allow some current coming from other internal power rails.
I could not find any information regarding this... My next step will be experimentation 🙂
Any help will be welcome,
Thanks, Marco
Show LessHello there,
I have a custom board using a PDM output digital mic running into the CY8C5667LTI-LP009 MCU. I use a slightly edited version of the source code found here. I programmed the MCU using the MiniProg3 over SWD with the Cypress Programmer 3.23.1 and it all seemed to go smoothly. However, when I plug in the board via USB to a mac or PC the thing doesn't enumerate. Does anyone have any nuggets of info on why this might be happening?
Is there some special way to program the MCU so that it will enumerate as a USB audio device or should it work when programmed the way I mention?
Ive attached the schematic in case that helps.
Any help would be much appreciated and virtual beer tokens can be sent!
Charlie
Show LessHello,
I will be building a firmware burner (jig) for the PSoC 3 (48 SSOP). What are minimum required connections for burning the firmware with the miniprog3? I know pins 25 through 29 are required for the miniprog3. Also I believe Vddd (pins 14 and 36) and Vssd (pins 13 and 37) connected to +5v and ground are required. Are any other voltage sources required for burning the firmware?
Regards,
Ron
Show LessHello Everybody,
I got a new psoc CY8CKIT 059 and I saw that it has 2 boards connected and it has 2 psoc ( one on each board ). I looked in the user manual and there said that this little "bridge" can be broken in two pieces if the developer wishes. So, why I would do that? What is the main functionality of each part? After I brake it I could program the psoc parts again ?
Show Less