PSoC™ 5, 3 & 1 Forum Discussions
Hi Guys, (and Gals, (and Those)),
I am using PSoC Creater 4.4 with a CY8CKIT-059 Prototyping Kit.
I am unable to locate example code "USBFS-UART" in PSoC Creator.
Pease help me with a link to this example.
Chuck
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Hey community, I hope creating a new topic will arouse more attention for my problem. Does anybody have any experience to measure the impedance using the AD5933 and a PSoC? I managed to measure the temperature with the AD5933 and read out the results. But I am in despair, not able to use the takeaway from the temp measurement for the impedance measurement. Maybe someone has some advice or code with a similar device from the company "analog devices". Thank you in advance, Alex
Show Less1) Implement an interrupt-based program for LED brightness change using a PWM module to Gradually, increase the brightness of the LED from zero to maximum in 3 seconds. And turn off the LED for the next two seconds.
2) Repeat this pattern periodically.
Please help how to do this step by step on PSoc Creator4.4?
Hello,
We are using PSoC LP5. I found in all our designs, pin 40, 41, and pin 57 --- pin62 are not connected to anything at all. I wonder why it is like that? Are those pins somewhat for special purpose?
Now we are short of GPIO pins, can we use some of those pins as GPIO?
Regards,
Yan
Show LessHello,
We are using a PSoC5LP and just implemented our bootloader. We are going to program the bootloadable application via the i2c bus from another microcontroller.
The other microcontroller is responsible for sending a "Reset" command to the PSOC to get it into bootloader mode.
What is the correct sequence in the PSOC for the bootloadable application to issue a reset command so it can go into the bootloader, and then wait for the specified host link time in the bootloader?
This forum post [Link] says to do the following in the bootloadable application:
Bootloadable_SET_RUN_TYPE(Bootloadable_SCHEDULE_BTLDR);
CySoftwareReset();
However, when I browsed the generated source code of Bootloader.c, it appears that if SCHEDULE_BTLDER is set, then it will wait forever for the command, and not even check the wait time set in the bootloader component.
If CySoftwareReset() is used without setting the run type, does the PSOC reset to the bootloadable or bootloader?
We used a PSOC4 in a different application, and our reset process was to enable the watchdog so we could reset from that. PSOC5LP is different, because the watchdog API is not as flexible as the PSOC4. Our watchdog is already going to monitor the application, and the timeout is too much for us to use for this purpose.
Show Lessi am using a Kit-059 as an SPIM to write 256 bits to a cross-point switch that uses a serial data stream interface (data and clock). the cross-point switch does not (specifically) use SPI, so there is no chip select (ss).
the cross-point switch is an analog devices AD75019
i have been examining the SPI signals with an oscilloscope.
i have attached the current state of said project. the immediate goal is to get some output from the processor.
the next goal would be to get more data transferred, so ultimately get all 256 bits transferred.
there have been various incarnations over the last few days, none with any output at xp_data, nor has xp_ss ever gone low.
a variant using three wires - bidirectional data lines instead of miso/mosi data lines also did not work
An attempt to transmit a few bytes, as done in SPIM Example Project 1.10 also failed.
clearly, i am missing something (many things??)
so, a few specific questions:
1) since my slave component (AD75019) does not use the chip select (ss), but i need it connected, what do i connect it to? or is it sufficient to take it to a pin, so the requirement that it be connected appears to be satisfied?
2) what is missing in the configuration files?
3) what is missing in the main program to tell the processor what to transmit and when?
4) is there a better example?
thank you
Show LessHello,
I am using an external microcontroller to write to the bootloader on a PSOC5LP via the i2c interface. I have successfully compiled the .c files provided by Infineon for the bootloader and I can successfully write the new bootloadable image to the PSOC.
However, I am having a trial-and-error approach when it comes to delays between writes and reads.
The internal code for transferring data has no delay between the write and read.
I have found that if I do not add a delay after the write in the WriteData callback function, then the program will fail immediately because the PSOC does not have time to fill its i2c buffer before the external microcontroller calls the ReadData callback function.
I want to be able to program as fast as possible, so I started experimenting with different delays after writing. I found that if I use a delay of 15 milliseconds after each write, then the program-row reads all come back successful. However, I believe one of the last commands after programming is to verify the application, and it seems like the PSOC takes longer to respond to that command. If I use the delay of 15 milliseconds, which works fine for all rows, then the last command always fails because the PSOC responds with all 0xFF's (I don't think the PSOC finished verifying the application, or whatever function it was doing).
If I set the delay to 50 milliseconds after each write, then it successfully programs, and the last command passes as well.
However, I want to be able to program the new image as fast-as-possible, and it seems I only need that 50 ms delay for the final write.
What is the recommended method for i2c programming as far as delaying the read until the PSOC is ready? Is there a GPIO that could be toggled so my external micro knows that the PSOC has filled the i2c buffer? The "TransferData" command inside the PSOC source files has no indication of what type of packet it is sending, so I am not sure how I could add logic to delay a different amount based on what type of command is being requested.
Is there an option inside the reprogramming source code for retry attempts?
Thanks,
Jason
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What is the future of the psoc5lp? Is it being abandoned?
Dear community,
I've been working with ADC sigma delta in resolution of 18 bits. I need to rest 2 signals (differential signals), like 2-5mV ac signals. Despite they're very small I need to put them over an offset, in this case of 1.024V available from psoc, 'cos I want to preserve low level of noise as suggestions observed in AN84783 page 11 : Input ± Vref to have the lowest noise and I can't bypass the buffer 'cos I have observed offset falls to 0.980V but even when I change to rail to rail or level shifter there are no changes; offset still falls.
In page 9 of reference document of ADC Delta-Sigma 3.30 the range with Input ± Vref with my Vref=1.024V on offset also should be: -1.024±1.024= 0V to 2.048. With all of these considerations I have the next questions:
1.- Why in example of CE95271 with the same condition as I, in page 2 says that if positive enter of ADC is 0 the converted value is -1.024? or if is 1.024 the value is 0? so the range doesn't go from 0V to 2.048 as page 9 of ADC Delta-Sigma 3.30? Please clarify this I'm very confused.
2.-. I have read there's a example of how to manage negative voltages on psoc, blog that I couldn't find unfortunately, but is related on applying offset, in this case 1.024 as AGND. Could you tell me where I can find this: http://www.cypress.com/blog/psoc-hacker-blog/measuring-negative-voltage-using-psoc1????
3.- Is it possible to interface directly these signals without offset moving input reference as low as Input ± 0.0625 * Vref?
4.- Do you suggest is better implement an instrumental amplifier with pga's and opamps instead of using ADC Delta-sigma? or in worst case an external INA?
I hope you can help me with your promptly response, thanks in advance.
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