PSoC™ 5, 3 & 1 Forum Discussions
Some data packets are seemed to be missing in serial reception from Neurosky mindwave mobile sensor at 57600 baudrate. I don't know if it is due to actual baudrate in PSoC4 57143 UART standard mode.Please help me to fix this issue.
Show Lessi want to do 6 channel clock output (60 deg phase shifted phase shifted fixed
frequency 100 Khz with 100nS Fix on time)
for this if i can make Jonson counter in PSOC 5 lp using UDB with 400Khz input
clock and its output AND with 400Khz clock, my work done.
Hello,
I'm debugging a odd little error on a sensor project I'm working on. My project is running current through external loads with IDACs, and taking sample with ADCs, all happen on timer interupts. Other than to run a IDAC changer, or take a sample and write it to Eeprom, the device remains in AltActive mode with as many things turned off as possible. (Can't go to sleep unfortunately because IDACs don't run in sleep mode).
Every once in a while, not at all frequently, my sensor seems to hang, get stuck, and never change its outputs/take samples (which I log and read later), until a power refresh.
Unfortunately, the project has a number of timer interrupts that don't play nicely with debug mode, so I'm mostly using GPIO (and led) debugging methods. So I haven't pinned down yet what might be causing this, mostly because it's so infrequent.
Anyway, my question after all this was that I use the ADC_DelSig_1_IsEndConversion(ADC_DelSig_1_WAIT_FOR_RESULT); api to wait for samples before writing it eeprom.
Can this API, or in general the ADC, ever hang indefintely?
Note: I do play with my clock speeds. I turn speeds down, then turn them back up before turning ADCs on, then after sampling is finished turn them down again.
Really, just asking question to locate or eliminate possible sources of the bug. This is one of the few blocking statements in my code, so was just trying to figure out if it could be a source of trouble.
Show LessHi,
I'm using the CY8C21534 and have a few questions about the tuning process of the capsense CSD user module. Can someone help me with these?
- in the tuning process flowchart ( CY8C21x34/B CapSense® Design Guide page 32 ) it is stated that the SNR should be between 5 and 8. In all other documentation I only found that the minium is 5 with no maximum given. What is the problem if the SNR is higher then 8?
- in that same flowchart the Ref Value is set to 2. In what case should this value be changed to an higher value?
Thanks.
Danny
Show LessHello everyone,
I'm designing system conditioning for a strain gauge transducer, I want a gain of about 200. the transducer power (Excitation voltage) I use from the PSoC itself of about 5 volt the output of the strainguage is connected to an Op-amp using different power options.
The problem is that when I use voltage from the VR for instance everything is alright but when I connect the output terminal of the transducer the voltage across them change and the output become fixed no matter I change the strain of the transducer.
Please assist.
maxdamage.
Show LessHello, I am trying to create an accurate millisecond stopwatch which records the timing of external triggers. I would like to be able to record hours long samples but accurately time the stopwatch down to milliseconds.
At the moment, I feel like my counter (see attached) is not recording accurately.
For testing, my project has an internal 1s PWM, which when measured on a scope is quite accurate.
This PWM fires an interrupt, which reads my Counter (which counts on an 1kHz clock). The main loop then prints this count number to my LCD, as well as the difference from the previous reading. I have as minimal work between interrupt fire and counter read as I can.
The problem is, when I print the difference to my screen for the every 1s count read, I consistently get a difference of 993 counts, instead of the 1000 counts I expect.
Can anyone offer any advice on how to improve the accuracy of my stopwatch counter?
Show LessI’m having trouble with the Timer 3.0 (16-bit UDB) for PSoC 5LP.
What is the intended function of the compare bit in the status register?
The datasheet says it’s sticky, so it gets set to 1 when the compare condition goes TRUE, but if the compare condition remains true, does reading the status register clear the bit, or should it remain 1? My problem is that the compare condition is true (I believe), but when I read the status register the CMP bit is false.
StepCounter_COUNTER=,0x0000,
StepCounter_PERIOD=,0xFFFE,
StepCounter_COMPARE=,0x000A,
StepCounter_Control_Reg=,0x82,
StepCounter_STATUS_MASK=,0x01,
StepCounter_STATUS_AUX_CTRL=,0x10,
Thank you.
Show LessHi all, i'm trying to transfer content of an array (SRAM) to a ControlRegister via DMA CPU Request, i'm trying to transfer 1 element of the array per request, but i haven't been able to do it, it seems like it transfer all the array per request.
I understand that if i set REQUEST_PER_BURST to 1 it makes the DMA Controller to transfer 1 byte per request, so i ask for a transfer every 500ms, but when i read the content of the ControlRegister on the DMA Transfer Completed interrupt i read the last element of my array and not the element i'm expecting, as i say i'm expecting transfer 1 element per request, not all 10.
Does anybody had test this kind of transfer?
I haven't found any example or question similar on the forum, find project attached.
Thanks in advance
Carlos
Show LessHi, I'm designing a 'hardware only' 3 channel DAQ system using an Analog Mux, DelSig ADC, and DMA. The ADC is hardware triggered at a 500us rate, with a channel sample rate about 20 times faster. (I'm sampling a 3PH power line). A uint16 by 3Channel by 1K circular software buffer is filled via DMA. The hardware and DMA are working just fine.
My problem is at some asynchronous time, a hardware interrupt is generated and I need to transfer the ADC circular software buffer to another memory location for processing. To do this I need a Head Pointer into the buffer. The PSoC 4200M has the API function 'CyDmaGetDescriptorStatus' which returns the CYDMA_TRANSFER_INDEX from the Transaction Descriptor. I need this functionality from the PSoC 5LP DMA v1.70 component.
2nd, (less Important question) Is it possible to configure multiple linked TD's that would allow DMA to fill 3 separate uint16 by 1K circular ADC buffers, (one for each channel), so I don't have to deal with interleaved channel data in software? I have reviewed the 'DelSig_16Channel' example but it is 1-dimensional: (1 sample per channel), I need a 2-dimensional solution: ( 3ea 1K circular buffers).
Note: the ADC circular software buffer is always full, so I don't need a Tail Pointer, and I don't want any ISR involved with the hardware ADC sampling.
Any suggestions?
Thanks,
Gary Beam
Show LessHi all,
I've somewhat successfully integrated the emfile component into my project and exported my data to my SD card. I am currently not meeting my time constraints and I am receiving gapping data on the sd card because of the lengthy writes.
I have 3x44kB arrays I need transferred ever second, after sending that through sprintf() with commas and whatnot that turns into around 250kB+ per second.. is this possible? I would assume it is but I cannot make it work with the emfile component. Am I missing something?
I did come across other libraries that claim to have better read/write times it seems (here: https://code.google.com/p/psoc3-5-sdcard-library/ ), but I would rather not go to the trouble of all that if the emfile could be modified/adjusted in a way to make it work. Even those still sound slow compared to modern SD r/w speeds. I am using a class 10 micro which is capable of up to 10MB/s
thanks in advance,
scarlson
Show Less