PSoC™ 5, 3 & 1 Forum Discussions
Hi,
has anyone used the CMSIS-DSP RFFT_Q15 implementation yet? Currently I'm feeding it with predefined values to check if I understand it correctly, but the output has negative values for the frequency bins, and I don't know why. For my understanding the output should be only positive values.
Regards,
Ralf
Show LessHi All,
Im looking at using a PSOC5 in a new project , and spent a wek or so reading up, and writing test apps. Got an idea now how most things (that I need ) can be done, but not DMAing or FIFO filling a data latch input of more than 8 bits ( using Dtype and status register) say up to 32 bit.
Has somebody created such a component? I would have thought it would be a useful addition to the components library
No doubt there will be lots more posts when I discover what I thought I understood is wrong!!
Many thanks
Steve
Show LessTerminals "Clock.clock_out" connected to signal "Net_75" have mismatching types.
i got this error while i connected clock source to anolog pin. what is way to out of this error
Regards
Rajendra
Show LessHello!
I would like to get a little help to build a onchip IA with PSoC 5LP. I made a search and found this excellent article http://www.cypress.com/file/53376/download. I repeated the Figure 3 circuit and it worked well for Vp = 400 mV and Vn = Vss. But let suppose that need to amplify a signal 3000 times, how would I do ?
Show LessHi all,
I am facing a bring-up issue with a custom designed electronic assembly that is based on a CY5668LTI-LP014 IC in QFN-68.
Here is a quick description of the psoc project:
* The f/w program is a stand-alone application, it implements a basic configuration of a few digital input and output pins.
* The psoc project operates with internal ILO and IMO, no use of the crystal oscillators. It also does not make use of the internal boost converter since the IC is powered from externally regulated voltage source.
* All analog, logic core, i/o voltages seem OK and are @3.3V with low noise ~50mVpp.
* All analog and digital voltages and which are generated by the IC seem correct level ~0.9V, negligible noise and are externally de-coupled.
* Single H/W reset asserts/de-asserts as intended during device programming and user interaction, via dedicated XRESn pin (no use of 2nd optional pin).
* Device Flash NVM successfully programmed/verified using JTAG in self-powered mode.
Despite this, the firmware program fails to start-up and activate/toggle the digital i/o ports of the IC. For narrowing down the issue i have also connected the internal ILO (100kHZ) to one of the digital ports; the port assumes the correct start-up level (high or low as configured in the psoc project schematic) but the expected AC signal of the ILO is not appearing after power-up.
My conclusion is that something is interfering with internal ILO to start-up and prevents the program code to be copied form flash and execute.
My questions are:
Are there any configuration settings/trims which might affect the operation of the ILO, or brown-out detectors and which can be manipulated in the psoc project or fitter settings ?
Are there are any techniques which i can use to gain any insights as to what is preventing the embedded MCU to start up upon power-on and hardware reset ?
Thank you
Kostas
PS: Attached is the project schematic
Show LessHi,
thanks to the community I've solved many problems but this one made me desperate.
My project is controlling speed of a low power brushed dc motor by controlling openning of a mosfet transistor. I prototyped it with development kit-001 and psoc3 but due to the cost I have to move to psoc1.
None of my trial to start DAC working succeeded. I have gone through lots of appnotes and datasheets but still no luck. My project has to go to the PCB stage but I have no luck with choosing chip - PSOC3 is expensive but PSOC1 is not working.
Cypress support is no help for me - they tend to reply once per 10 days with most ideas not relative to my project. I get more surveys from them then help.
Lately I followed psoc1 example#3 "ADC to UART with DAC" just to make sure I do everithing right but again DAC not working. I think, I missed something because compiled example is working.
Attached project is my trial to follow the examle with the same hardware settings and copied main.c - and still doesn't work. I can't understand that.
Any help is greatly appreciated,
Oleg
and another questions: any ideas what the output impedance of the dac? do I have to buffer it with opamp in order to control gate of a mosfet?
Show LessI switched srams, to a 16 bit sram with 18 address bits and now I cannot read/write to the external sram when I'm accessing anything using the msb (addr bits 16 and 17).
I found when I disconnect the 16 and 17 addr bits and tie them either high or low it works fine, but when its connected to the psoc and being selected by the emif component it displays the same thing on the lcd (i get changing values when its accessing only the lower 0-15 addrs bits or if 16 and 17 are not connected).
this is consistent across gpio pins.
I'm using 512kbx16 sram: CY7C1041D
Its almost as if the way the psoc is interacting with the sram is messing it up somehow.
Does anyone know what is going on?
Show LessI've been using DMA in several projects lately, all working fine after some trial and error, but I'm using a slightly different project and now it won't work.
my DMA reads in the different values from the SPIM component's rx ptr (I have done this several times) but instead of putting them into one array, it separates each 32 bits into 3 different arrays (every 32 bits goes to 1 of the 3 arrays). It does this by using some verilog to multiplex through which DMA the SPIM_rx_INT triggers.
I have verified the verilog component is working properly and with zero delay, but for some reason when I have it inside my project the DMAs do not seem to transfer anything, and the TD done output is never set.
I previously had a similar setup where I had the
SPIM>DMA(3 TDs each with a 32bit value) >verilog to sequence DMAs creating the arrays>3 DMAs to create 32-bit arrays,
and this setup worked just fine, but I wanted to switch my setup around to free up some DMAs and stop wasting time reading/writing from sram.
What I want to have is,
SPIM>verilog to sequence DMAs creating arrays>3 DMAs to create 32-bit arrays.
but the DMAs are not transferring for some reason
I am posting my project here, if someone feels generous I would appreciate it if they could give their input, I am out of ideas for where to look.
Show Less