PSoC™ 5, 3 & 1 Forum Discussions
On one of our boards we need many pins with VDDIO = 1.8V.
We have a 1.8V converter on board, but it should be equipped with an enable input, as
it powers many other components.
The PSoC is powered from and external 3.3V source.
In order to avoid the dependence on an external 1.8V source I wonder whether we
could power one VDDIO-bank from the internal regulator for digital logic, VCCD.
The data sheet says: "The regulator output is not designed to drive external
circuits.", but would VDDIO qualify as "external circuit"?
I could think of using two Shottky diodes and supplying VDDIO from the onboard regulator when it is up,
and use VCCD only to get enough supply to activate the enable output.
Andreas
Show Lessi attached my project and input circuit of thermocouple.
my project is working perfect but i got 2048 as offset in 12 bit adc means i got half adc resolution as offset so my whole temperenge range of thermocouple is not covering in this adc.
can anyone tell me where i made mistake in my code???
basically i made this project from cypress 2148 appnote but i did not used low pass filter which is said in appnote but i made it physically as a external circuit.
Show LessHello,
I have to program ten PsoC 5 chips with PSoC programmer 3.42.2 and Mini prog3
PSoC programmer fails to program 3 of 10 chips,
but Seven chips is programmed successfully.
The error massage is "Timeout of SPC polling "
My conditions and configurations are as follows,
=======================
CY8C5868AXI-LP032.
Programming Mode: Reset
Verification : On
Auto Detection: On
Protocol: SWD
Voltage: 3.3 V
Connector 5p
Clock Speed 6MHz
======================
What Should I do ?
Best Regards,
Show LessIn a PSoC 3 design I need a differential amplifier but it does not seem to work.
I created a simpler design for the CY8CKIT-030 (as attached):
Two voltage VDACs drive the two inputs of a PGA the output of the PGA can be observed through
a voltmeter and the ADC.
I can control the VDACs and PGA settings through USB.
I checked the settings of the PGAs (PGA_1 in the schematic is implemented by SC0 as seen by the chip so the
relevant registers are 0x5800 pp):
0x5800:
'0x0c', '0x2e', '0x01', '0x00'
So the GNDREF - field in SC0_CR2 is 0, which -- according to the register TRM means the external input is used.
And still, the output of my circuit depends only on the voltage of VDAC8_1, i.e. the positive input of the PGA.
The output is as if the reference input was at 0.
I also checked the analog routing representation and this seems to be correct, the output of SC2 goes to the input of SC0.
I did not find many examples that use the PGA, but maybe someone in the forum has more experience with them.
If not, I need to open a case, I guess.
Andreas
Show LessIs there any information on using the CAN Bus as the communication port for Bootloader in PSOC5LP?
Hello Every one,
I am making communication between Pi and PSOC.
What i am doing is the following:
My Pi is sending me a 2 bytes of data (16 bits). I am reading that data and performing a logical and operation and sending my filter data back.
Please find attachment and have a look on my program and give me your valuable suggestions.
Looking forward for your reply.
Regards
Awais
Show LessHi.
Just one question. How can I using DMA put data from PSoC SRAM to registers in ALU, for example I want to send uint8 byte to A1 register without using ARM processor - that means without using this code ' component01_<ALU_1>__A1_REG = byte;'.
With regards.
Show LessHello All,
Every time if i want to transfer data from ADC_SAR to VDAC via DMA. I always get this notification in red (see attachment) when using DMA wizard.
Can any body help me regarding this?
Regards
Awais
Show LessI played with psoc5 LP, and I didn't found content that clear explain the psoc conceptual idea on a clear way.
I make some conclusions that and don't know if they are right or not.
Psoc have 3 main pillars.
1) Some kind of auto generated HDL based on graphics components, lets say this is the hardware platform like one modular analog / digital fpga that will be made by some kind of syntheses.
2) A auto generated C base code to interact with the hardware layer based on the component creator idea and definitions.
3) The user arm C code that will call your own routines and also the auto generated code.
Am I right ?
Where can I found information on this conceptual idea ?
Show Less