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PSoC™ 5, 3 & 1 Forum Discussions

Anonymous
PSoC™ 5, 3 & 1
Hi everybody..    I am trying to receive 3 words of 16 bit each in a SPI slave from a master using interrupt on the slave side. Both master and slave ... Show More
Anonymous
PSoC™ 5, 3 & 1
 I had an old Invention Board (circa 2003), which I'm finally getting back to. However, it didn't ship with drivers for Win7....    Digging around abo... Show More
WaMa_286156
PSoC™ 5, 3 & 1
  I would like to convert and move 8 bit data in one SRAM buffer into 16 bit data in another SRAM buffer.  The data bytes can be twinned, as I will be... Show More
KeYp_290406
PSoC™ 5, 3 & 1
When setting the flash protection for a bootloader on a psoc 3 project it's easy to find the bootloader flash start and end from the map file. The map... Show More
Anonymous
PSoC™ 5, 3 & 1
Hello my name is Felipe and i know the Psoc 1 is a litlle bit obsolet but i think for some case it's ok, anyway i've tried to create a software Pwm, b... Show More
Anonymous
PSoC™ 5, 3 & 1
Hi,    I am working on power line communication on CY3274 development board , and wanted to use i2c protocol to communicate with the I/O expander but ... Show More
DaRe_2236336
PSoC™ 5, 3 & 1
Is there a way to read a CAN bus mailbox ID that has been set in the configuration window? I know I can use    CY_SET_REG32((reg32 *)&CAN_TX[mailbox].... Show More
Anonymous
PSoC™ 5, 3 & 1
Hi,    I'm having a problem getting the bootloader working when compiling under Creator 4.0.    The code has maths functions in and compiles with no b... Show More
Anonymous
PSoC™ 5, 3 & 1
I got a tip that Cypress PSoC could suit my needs. Now I have a few questions to ask.    I have three signal channels all of which will receive a sign... Show More
Anonymous
PSoC™ 5, 3 & 1
Hi,    I’ve been working on I2C communication between a PSOC 5LP (master) and multiple PSOC 4’s (slaves). This is being done with a Cy8CKIT-059 and mu... Show More
Forum Information

PSoC™ 5, 3 & 1

The PSoC™ 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.