PSoC™ 5, 3 & 1 Forum Discussions
I need to modify the default 8 1 N string of the UART transmitter possible in the PSOC 1 devices. The requirement is for 7 2 N format. Does any one know the solution as cypress tech support apparently is not interested in looking in such trivial matters. I would be glad if some one could help me.
Show LessUsing the Fixed-Function I2C Slave component on PSoC5LP, is there any way to get an interrupt when the Master writes? The only way I have found to know if the Slave has received data from the Master is to poll the Slave's status register and look for I2C_SSTAT_WR_BUSY or I2C_CFG_REG bits. I need to respond quickly, but don't want to waste all my processor time polling the register.
Is there any callback function I can use, or a way to enable an interrupt pin?
Thanks!
-Will
after a little reading and studying about PSOC 5, I discovered that there are 2x SAR ADC, 1x Del Sig ADC, 1x Sample and hold circuit. This is very small amount of ADC.
I have 6 sensors, their output is AC signals (sine wave), I want to connect them to psoc5lp and then detect the maximum peak for each signal, then send the peaks values to the computer by UART. Is it impossible to do this tasks thru chip, right?
Also I need to generate a sine wave this 20khz frequency inside the chip, then connect the signal with an analog pin, which connected to a seventh sensor, after that, re-enter this signal to the chip to do sample and hold on it, is this possible to do on psoc5lp, cy8c888AXi???
Show Lessif i have multi variables integer x1 ,x2 ,x3 , x4 ,x5 .
x1 from [ 0 , 10] => the corresponding voltage = 1 v dc on P0[1]
x2 from [ 10 , 20] => the corresponding voltage = 2 v dc on P0[2]
x3 from [ 20 , 30] => the corresponding voltage = 3 v dc on P0[3]
x4 from [ 30, 40] => the corresponding voltage = 4v dc on P0[4]
x5 from [ 40 , 50] => the corresponding voltage = 5 v dc on P0[5]
i want to transfer each corresponding voltage its equivalent pins using psoc5lp ???
are there av application note , idea or algorithm about this???
thanks
Show LessHi all,
I am still just doing the lessons from the PSOC 101, and i am stuck at I2C, Bridge Control Panel does not list my device.
I ve tried all ports available in cydwr.
The 2x6 female header for the debugger does seem to provide dedicated I2C Pins.
I noticed after some re-read of sparkfuns intro that there are I2C jumpers. Is this the solution?
Board:
https://learn.sparkfun.com/tutorials/freesoc2-introduction
Lesson:
https://www.youtube.com/watch?v=ks_48gjCBNc&index=11&list=PLX6sqqUB8iOjsMfGEDcsPSuYLEFCh50Hr
Show Lesspsoc 5
i am going to purchase psoc 5 chip, but i am confused to select the type.
i need a chip with maximum analog blocks , previously i worked on psoc cy8c29466 24pxi , there are 12 analog block, i was planning to build a big project on it .
but the analog blocks are limited ( ex , i can't put more than 4 analog continuous time like 2 pga,1 comparator , 1 refmux and then all the CT blocks are full , so no analog input can come into the chip )
i want more than this number of CT bloks .,, which type of psoc 5 chip allowed me do a lot of analog tasks without fear from available space ???
image below shows a small part of the project , i need more analog input , more CT blocks , more analog blocks ,
the analog apace is full now , what is the best choice of psoc5 chip to do all my project on it ?
Show LessNow things get really interesting! I have a datapath-based component (you helped me to develop it in the Parallel port thread). Its function is as follows: idle a trigger arrives (51kHz if that matters). Then issue 9 consecutive DMA transfers on the same channel to an 8-bit GPIO port, generating externally visible strobes after each transfer. and sampling the status of an external 1-bit input (through the carry chain), collects the last 8 results and store the final 8 bits into an output FIFO. The datapath FSM manages all that. This, together with a Count7-based fixed duty cycle two channel (with deadbanding) 500kHz PWM generator fits within a single UDB.
The question is about triggering. The trigger signal pulse will have unknown duration (now 50% @ f=1/51kHz, which is long in terms of the 64MHz datapath clock), but synchronized, so a resettable edge detector is required. It can be easily written in Verilog, but it would eat up one PLD macrocell. So I've invented the following: since one FIFO is unused, it could be configured to internal dynamic mode (d1_load=0). Then its write strobe (f1_load) is connected to the trigger signal, the write data source could be anything except of CPU/DMA, according to the manual (now: A1) and f1_bus_stat indicates whether the FIFO is not empty. Then the system starts with f1_bus_stat high (empty FIFO), the trigger causes it to load something into the FIFO (the fetched value has no meaning), f1_bus_stat gets low and datapath starts its job. In the final state D1 is loaded from the FIFO, which makes it empty again. The result is a resettable edge detector based on the FIFO; moreover, it can buffer up to 4 trigger signals should they arrive before the datapath's job completion (cannot happen here, but still a potentially useful feature).
The scope confirms it works like a charm, but since it abuses the FIFO so much beyond its designed purpose, there is a question whether the whole approach is legal in terms of the specification.
Show LessMicrocontroller: PSoC 5LP Prototyping Kit
I am building a linear measuring device, it will measure the travel of a 40 foot long table on a large milling machine.
It will have a resolution of 0.0005 inch so I am using an encoder strip with 2000 LPI ( lines per inch).
A distance of 40 feet (480 inches) at 0.0005 inch from one encoder strip line marking to the next equals: 480 inch / 0.0005 = 960,000 pulses in 480 inches
So it will take a minimum of a 20 bit number to represent the full travel of 480 inches - ( LOG(960000) / LOG(2) = 19.87 bits )
A 20 bit number should allow me to have a value of 2^20 = 1,048,576 which is greater than my required 960,000.
That is why I need the Quadrature Decoder in 32 bit mode.
According to the data sheet:
The ranges for counting are the following:
> 8-bit counter: -128 to +127
> 16-bit counter: -32,768 to +32,767
> 32-bit counter: -2,147,483,648 to +2,147,483,647
So I should be able to get a count of 2,147,486,647 in the positive direction but when I run the project it only counts to 32,767 and then resets back to zero.
I also found this in the data sheet:
The 32-bit counter implements the lower 16 bits in the hardware counter and the upper 16 bits in software to reduce hardware resource use. For this target, an additional ISR is used. To work properly with the 32-bit counter, interrupts must be enabled. You can add ISR code to source files as needed; see the Interrupt Component datasheet for more details.
So my question is: how do I do that? Right now I have no clue as to where/how to start, will someone help?
Doug
Show LessHello,
finally I am at the component's interface polishing stage (see the attached project). I want to setup the symbol parameters correctly and provide the user as much information as I can, so here are my questions:
1. The component has the 'clock' terminal, which currently can be manually configured as NCO_CLOCK_FREQUENCY. I want it to work automatically, so how do I infer the frequency of the clock routed to this pin? The Cypress ADC component somehow can do it in external clock mode -- the sample rate is derived from the connection.
2. From NCO_CLOCK_FREQUENCY and NCO_DEFAULT_FREQUENCY I can derive NCO_MIN_FREQUENCY and NCO_MAX_FREQUENCY. I would like to display their values to the user (in read-only mode), but if I move their definitions to the 'Formals' section, there is a problem. For some unknown reason Creator enforces parameter definitions in alphabetic order, so the MIN/MAX params are defined after NCO_DEFAULT_FREQUENCY, which derails its validators. How to work this issue around (without renaming the params, of course, as it is not very elegant)?
3. NCO_DEFAULT_DDS_INCREMENT is also calculated as an uint16. How do I extract its high/low bytesin Verilog to compute datapath registers' initialization values? Currently I provide two more auxiliary params, but I don't like this solution:
.d0_init_a(NCO_DEFAULT_DDS_INCREMENT_LO),
.d1_init_a(NCO_DEFAULT_DDS_INCREMENT_HI),
4. In MainsNCO.c I refer to the values of some hardware flags, e.g. the Count7 start flag or define the following FIFO flags:
#define FIFO0_CLR 0b00000001
#define FIFO1_CLR 0b00000010
#define FIFO0_LVL 0b00000100
#define FIFO1_LVL 0b00001000
I believe they are already defined somewhere, so there is no need to twiddle with their bit encodings, but I am unable to find them. What would be their names and, more importantly, how do you find them? (I think it is the 'where is ResourceMeter' kind of question, but anyway 🙂 ).
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