PSoC™ 5, 3 & 1 Forum Discussions

I need a 3mbps UART, but I also want to run my PSoC5 at 64MHz. This creates a conflict, because a 3mbps UART needs either a 24MHz or a 48MHz clock, and so I can't use a 64MHz master clock. (It's a shame I can't get access to the 48MHz USB clock).

One way around this would be to create a 4/3 or 8/3 clock divider. I've looked online, but can't find any examples of how to do this.  Does anyone know if it's possible to do such a thing in Verilog?

Many thanks - Hugo

I'm trying to get basic project working to measure flight time between ultrasonic transmitter and receiver. I'm using the -050 psoc 5lp dev kit.

The receiver signal goes through a PGA to a comparator. The signal coming out of the PGA looks fine and the Comparator output is as expected too. The comparator output connects to the timer capture input. An interrupt is triggered on timer capture which reads capture value and shuts down the timer and comparator. The measurement I'm getting is between 480-490 microseconds but you can see on the attached oscilliscope the real time between PWM start and Comparator high is actually ~440 microseconds.

Attached program has sync component between the comparator and timer. I've also tried without sync component and with sync option on comparator. Same result for all.

I've also tried just sending a test signal to the timer input by driving a pin low-high with a delay of 400us. With the test signal I get a correct value from the timer capture and also matches oscilliscope.

Is there something I'm missing here?

Thanks

Aaron

I need information on how exactly  EMIF_WP_WAIT_STATES and EMIF_RP_WAIT_STATES affect the EMIF timing. A timing diagram showing the EMIF timing with wait states is needed. Thanks!

Hi,

I have some problem with UART transmision. I'm workin in a project with TIA and a ADC. I have designed my own PCB with a PSOC chip. When a try to transmit by UART and I have the TIA and the ADC enable I don't recive correctly. But if I disable the TIA and the ADC I recive correctly.  I guess It should be something related with noise, but I don't know exactly what can be. Can anyone help me?

Thank you!

I wish to attach an external A/D to the PSOC5LP. The external A/D is running at 20MSPS and has an 8 bit parallel output. Would a EMIF and a DMA channel be the best bet?

How can I insert a note or a bit of text on a schematic diagram?  I want to note the significance or setting on a diagram.  Thanks

Does anyone know what the Reset input on the CRC component (V2.40) is supposed to do?  On page 2 of the data sheet I find the sentence "The reset input defines the signal to synchronous reset the CRC."  In the Component Changes section under version 2.0 an item reads "Asynchronous input signal reset is added."  However, it doesn't actually say what is reset.  Also, it contradicts itself (synchronous vs. asynchronous).

I had assumed that the reset line would either clear the seed/CRC register or load the seed value (which is 0 in my case), but it doesn't seem to do that.  I assert and de-assert the reset input before clocking in new data.  The first CRC is always correct, but subsequent CRCs are wrong.  However, if I write a zero to the seed register in software before the 2nd and subsequent data streams, the CRCs are always correct.  Thus, I believe the seed/CRC register is not getting reset by the Reset input.

Since the data sheet doesn't really tell what the Reset input does, I don't know if this is expected behavior or an undocumented "feature".  Does anyone know?

Paul