PSoC™ 5, 3 & 1 Forum Discussions

Hello, members.

I have a question about PSoC5LP Filter Component.

When I check the Custom coefficient, set the Filter class to FIR,

and set the same as the attached file (DFB Configuration FIR),

the value of Filter taps can not be changed from 2, and

when I check the Custom coefficient, set the Filter class to Biquad,

and set the same as the attached file (DFB Configuration Biquad),

the value of Order can not be changed from 2.

Why can not I change the value of Filter taps or Order from 2?

Also, how can I change the value of Filter taps or Order from 2?

Best Regards

I'd like to know maximum sample rate of ADC10.

Device is CY8C21123-24SXIT.

Current Data sheet mentions how to calculate sample rate.

But there is no maximum spec.

I can see maximum spec is 7.35 Ksps in old data sheet.

Please tell me maximum sample rate of ADC10.

Hello everyone!

When I new a empty project, I can't find cy8c55 family. My device is cy8c5568axi-060. So how to add the device? Is there a similar device instead?

thanks all.

Hello,

I want to filter  data which is stored in an array and send filtered data to uart.  The data transfer between UART and filter is done with the help of DMA,whose DMA request is generated from filter itlsef. Similarly array is transferred to filter input by another DMA,whose DMA request is generated from firmware.

The problem now is i am not getting anything on UART. How to debug this issue?

I have attached my project below.

Thanks in advance.

I'm running into odd problems with my design when I add extra gates to be driven from GPIO Pins. It looks sort of like a fanout issue. For instance, I have a R/W pin (low for write). It's a CMOS level Digital Input in my design. The solution works fine if this signal is connected to an AND gate input or a NOT input, but not if connected to both. I added a second NOT in series, so that the output from the first NOT could drive the AND gate (the pair acting like a buffer), and everything works again. It looks, in the case, like the extra load of both a NOT and an AND is too much for this R/W signal.

I would have thought, though, that the Pins themselves would act as buffers. There is actually an Input Buffer setting on the Input tab, and it is enabled.

There also is no buffer component in the palate, which again makes me think they should be needed.... but then why am I seeing this kind of behavior. I saw something similar when I connected another Digital Input pin to both a Status Register and a NOR gate. One or the other works, but not both.

This is on a CY8C5888.

Thanks,

Paul

I have edited my Clocks section in PSoC Creator to set my Master Clock to 48MHz, with a 3MHz IMO. 48MHz shows up everywhere here, but when I program the solution and review the timing.html file in results it shows 24MHz.

What do I need to do to get the faster clock to take effect?

Thanks,
Paul

Hello,

I'm trying to check the sample rate in the eoc pin of the Delta Sigma ADC. The ADC is hardware triggered with a pwm signal. The ADC is sampling and i want to know the exactly sample rate checking the EOC signal. However this pin is always LOW. It do not chage its state. How I can check this?

Thank you

I thought it was 0xFF but when I check the memory space during debugging, I see 0x00. What is the default value for internal EEPROM on PSOC5 LP?