PSoC™ 5, 3 & 1 Forum Discussions

hello i need to use the lcd multi port blick ,but for some reason icant use it , u get this eror :

is this becouse the verson of the LCD mp is older then my PSOC ?

I'm sending packets to the psoc with a custom bootloader application and the packets make it to the device however I'm getting the error message "the data is not in the proper form". My current application is a visual studio forms app where the first two command packets work as intended(see http://www.cypress.com/file/45171/download​ page 33), but when I send a packet, a byte array, i receive the previously mentioned error code. Since the error code is so general it is difficult to figure out exactly what the issue is. Feel free to ask any questions about my current setup or application

-Thanks

Adam Esche

I'm getting this warning: "Warning-1350: Asynchronous path(s) exist from "comm_clock(routed)" to "CyBUS_CLK". See the timing report for details"

Can someone help me resolve this?  My research indicates that I may have to use the Sync component but how do I do that?

I am trying to build a keyboard controller based around a PSoC5 CY8CKIT-059. It's mostly working really well, apart from one problem I've been unable to sort out.

The controller uses a keyboard matrix: a grid of horizontal probe lines connected to a ControlReg, which are grounded one at a time, connected via the keyswitches to vertical sense lines connected to a StatusReg. I detect a keypress by looking at the sense lines and correlating which ones move with which probe lines get grounded. Disconnected lines float high (I have the StatusReg set to pull up).

Here is an example. This is the status of a sense line with a key pressed on the keyboard. The corresponding probe line gets grounded for 1ms, and we get a nice crisp pulse in the sense line. This one is working fine.

However, one --- just one --- of my sense lines produces pulses which look like this. It's behaving as if there's a big capacitor connected to the line. Electrically it's almost identical, with no active components at all. Even the PCB traces go in roughly the same places; but it's taking multiple milliseconds for the voltage to rise back to the logic-high threshold. This is causing spurious keypresses. I tried connecting an additional pull-up resistor; this is 3K3, which is as low as I dare go at 5V, and it's still not rising fast enough.

Are there any internal components in the PSoC5 which might be causing this? I've had a look and don't see anything, but that doesn't mean much. The only difference between the two examples is that the good one is connected to P0[5] and the bad one to P0[4]; they're the same StatusReg, with identical settings: it's set to input only, pull up. Anything I'm missing?

I have a PSoC5 Prototyping board and am using the RTC.  When I disconnect the board from its power source the RTC looses it time setting; how do I get the RTC to maintain its time setting when powered down?

The initial part of the code is working very well, but after line 139/140 the ISR for sending data across UART/SBUS buggers off.  Up to that point it sends data correctly with a 6ms delay between frames, but after that point goes nuts and keeps sending data constantly without delay and it doesn't seem like anything else in the code is running then.  Its hard to check because if I use the debug and set break points it will get to and run past that point fine, but I can't use it after that point because the flight controller that the UART/SBUS is talking to will have had a fail safe due to too long of a delay between frames.  I can see what is happening though when I hook up my oscilloscope, so I know its sending the 3ms frames with 6ms delay to begin with, and then it goes nuts afterward sending a constant stream of data.  Not really sure what to do at this point.  I have tried everything I can think of as well as testing the Timer component in a separate project to test its functionality, and I can't seem to figure out what is going wrong, any help would be appreciated.  I need to get it running correctly so that I can start test flights and tuning the PID gains.  Attached is the project file.

Thank you

Hello guys,

I'm trying to figure out a way to sample just one cycle of a wave generated by the WaveDAC8 component.

So, my question is:

If the waveDAC output an 8-bit waveform (by my understanding, this means that the values it outputs are 8 bits long), and one cycle of my wave has 200 samples, how many samples will a 16-bit ADC get into one cycle?

I'm asking because I want to extract exactly one cycle.

The image attached has the schematic of the circuit being implemented.

I can connect a vref or a vdac output to an analog mux.  However, it appears that I can only connect a gpio pin to an ADC_SAR_Seg component.  The device is a 5lp.  

Am I doing something wrong or is this a limitation of the ADC_SAR_Seg component?

Thanks

Glenn Edgar

In ADC_SAR.c, why dose ADC_SAR_IsEndConversion() call CyDelayUs(1u) ?

I don't understand the meanig of comment /* wait one ADC clock to let the EOC status bit release */.

And, I can't find the detail of EOC status bit.