PSoC™ 5, 3 & 1 Forum Discussions

Hello

i am trying to design my own customized board kit depending on CY8CKIT-050 Board , i already downloaded files Schematic, Layout, Gerber, BOM attached in

http://www.cypress.com/documentation/development-kitsboards/cy8ckit-050-psoc-5lp-development-kit

i tried to open them in Eagle and Altium but they told me files are corrupted

please can you help me with that.

Is there a way to read Vddd and Vdda without using extra analog pins (and voltage divider)?

Running on power boost, and just need to monitor actual system voltages.

Thanks

Is it safe to use negedge clocking in PSOC Verilog.  I was concerned because AN82250 PSoC® 3 PSoC 4 and PSoC 5LP Implementing Programmable Logic Designs with Verilog, on page 13 says:

Note To reduce the likelihood of timing and synchronization failures, it is preferable to use posedge clocking in PSoC designs.

But no further detail on why the AppNote says this.   On the other The  Warp Verilog Reference Guide doesn't seem to mention anything against negedge, and uses it in several examples.

When designing for DDR style clocking from an external source, using both posedge and negedge clocks seem needed (or to resort to a significant oversampling using an internal clock.)     Is it reasonable to ignore AN882250's advice in this case, doing something like:

always @ (posedge clock) 
begin 
. . .  something
end

always @ (negedge clock) 
begin 
. . .  something else
end

?

PSoC® 3 PSoC 4 and PSoC 5LP Implementing Programmable Logic Designs with Verilog.pdf

As we are developing a measuring instrument we have selected CY8C27443-24PXI AND CY8C29466 -PXI .WHICH TOOLS ARE REQUIRED TO PROGRAM THESE TWO PSoC ?

Hi !

How long wil be produced the CY8cmbr3110 and the CY8cmbr3116?

Because I´m using this chip in your products. beste regards