PSoC™ 5, 3 & 1 Forum Discussions

Dear all,

I am wondering Can PSOC 5LP DMA generate a signal after each transfer (not finishing TDs)? I understand that NRQ can generate a signal of two clock cycles after the TDs is finished (I chained 16 TDs). I am asking because there are two DMA channels in parallel sharing the same spoke (DAC). They may or may not be at the same rate. I want to know when each transfer is done so I can align the signal. The master clock is 78MHz.

The signal I am trying to alian is the trigger out signal. So I generate a waveform from flash through dma to DAC and output to a GPIO. I want to generate a trigger signal which is aligned with the waveform to another GPIO. What I did is that I user a counter, and route the drq signal and count of the trigger together. I set the period of the counter to the number of points that DAC will output and compare threshold of the counter to be half of the number of the points in DAC. I then use the compare out as the trigger signal. I can get the trigger aligned when 2 DAC channel are used at maximum speed of 1Msps. When I set the update rate of both channel to 2Msps, the output signal in DAC and trigger are still correct in timing. However, the alignment is lost, and timing difference is keep shifting. In update rate between 1Msps and 2Msps, each time after the sequence is downloaded via USB, there is a chance that the alianment will miss but not each time.

I suspect it will be better if I can have access to the signal that each DMA transfer finishes as that will the be the exact time that I want to count in the counter.

Best,

I have already developed firmware that uses 16-bit, but now I need higher sampling rate so 14-bit is used.  I would like to keep one firmware that can work with either.  Is it possible to modify the resolution at run-time?

Hi All,

I have tried the power management_Hibernate code example for psoc5 lp family. I am using it in my Cy8c5888LTI-LP097 controller. I am able to go in hibernate mode without watchdog reset but when i try the same code example with watchdog timer, it is not working with it.. I already tried

        CyWdtStart(CYWDT_1024_TICKS,CYWDT_LPMODE_DISABLED); and

        CyWdtStart(CYWDT_1024_TICKS,CYWDT_LPMODE_MAXINTER);

API so that it will stop the watchdog in hibernate and sleep mode but it is not working in my case.

this is my case i am clearing WDT before entering hibernate mode.

if(Pin_1_Read() == 0) {

            /* Turn off LED to indicate Hibernate mode */

            LED_P1_2_Write(0u);

            CyWdtClear();

            /* Prepare system clocks for the Hibernate mode */

            CyPmSaveClocks();

            /* Switch to the Hibernate Mode */

            CyPmHibernate();

            /* Restore clocks' configuration */

            CyPmRestoreClocks();

            LED_P1_2_Write(1u);

        }

Any suggestion in this case.

Thanks in advance...

Regards
Abhishek

Hi,

With PSoC 5, I2C Master UDB configuration, I am interfacing to a Microchip 244AA64F EEPROM. My goal is to write information to the EEPROM, then read back to verifty. So far I have only been successful by using a fixed CyDelay() with a minimum of 4 milliseconds. The Microchip data sheet has a flowchart for ACK polling which I've attempted but my status from I2C is always I2C_MSTR_ERR_LB_NAK, then becomes I2C_MSTR_BUS_BUSY and never becomes I2C_MSTR_NO_ERROR.

Once the write has been performed a I2C_1_MasterSendStop()_is sent. Then I would like to somehow poll that the write cycle has completed and continue on.  The Microchip datasheet states that while a write cycle is in progress, the chip will not submit an ACK and recommends sending a start condition until the ACK is returned. This is how I've implemented it (unsuccessfully).

status = I2C_1_MasterSendStart(0x50, I2C_1_WRITE_XFER_MODE) ;

while(status != I2C_1_MSTR_NO_ERROR)

{

     I2C_1_MasterSendStart(0x50, I2C_1_WRITE_XFER_MODE) ;

}

Is there a simple, tried and true method for polling?

Thanks, Nick

Hi there all,

I've been working on creating an I2C Bootloader host application for PC using the CY7C65211 USB-Serial bridge IC aboard the CYUSBS234 Dev Kit.  I am attempting to bootload the PSoC5 on the CY8CKIT-050.

I finally got the USB-I2C API going in C# .NET (thanks to this thread) and now I'm running into errors during the actual data transfer processes.  When I attempt to bootload, I get an error code 0x4019.  This corresponds to the bootloader reporting an error (0x4000 is the mask), but I'm not sure where the 0x19 is coming from (it doesn't match to anything in the ReturnCodes enum).

I have a logic analyzer capture of the activity on the bus for the bootload process.

Transmission from Host (0x38 - Enter Bootloader):

Response from PSoC (??? - Where did those 0xFF bytes come from?):

Transmission from Host (0x3B Exit Bootloader):

At this point, the process ends with the 0x4019 error code.  The first thing I notice is that the second transmission (response from the PSoC) doesn't  to adhere to the response packet structure outlined in the Datasheet for the Bootloader v1.60 component.  I'm only getting what is presumably the Start of Packet (0x01) byte after 12 0xFF bytes.  I'm not getting the End of Packet (0x17) byte at all.

The twelve 0xFF bytes from the PSoC is almost certainly the issue, but at this point in the execution of the bootload routines, the process is basically out of my hands and in the domain of the bootloader component that's actually handling all the comms to the host.

The length of the start condition on the first transmission from the host and the length of the ACKs at the end of each transmission also seem a bit long, but shouldn't actually matter I don't think?

Any ideas for what I can check to narrow the issue down?  Something I'm getting wrong?  The bootloader on the PSoC should in theory just handle itself, I don't know why the response is the way it is.  I've attached the Creator project.  I can also provide the Visual Studio C# WinForms project I've been using to test this if need be.

Thanks,

-Kyle