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PSoC™ 5, 3 & 1 Forum Discussions

ghchc_4077826
PSoC™ 5, 3 & 1
Hello all,I have a question regarding the ultrasonic HC-SR04 sensors and PSoC.What I did until now:I followed up the example from here: Intro to Cypress (Part 2): 3 Steps... Show More
alro_2373731
PSoC™ 5, 3 & 1
I have 2 PSOC5LP DVKs with 10 pin JTAG headers on each.  I have wired them into a bread board connecting them via JTAG daisy chain schematic using the... Show More
moro_1580446
PSoC™ 5, 3 & 1
MRF24J40
solved msg Solved
Hi everybody.i want to run zigbee module(MRF24J40) with psoc5 and in spi mode.now i can initial module but i have some problem.MRF24j40 has a int pin ... Show More
cykec_294231
PSoC™ 5, 3 & 1
AN72845 Design Guidelines For Cypress Quad Flat No-Lead (QFN) Packaged Devices makes the following statement on page 16:Typically, QFN-packaged device... Show More
KyTr_1955226
PSoC™ 5, 3 & 1
Hi all,This is maybe more of an embedded C question than a PSoC specific question.I've got something I'm working on where I'm using a single timer to ... Show More
shsh_299891
PSoC™ 5, 3 & 1
Hi, We are using an IDAC at constant current, while the output current is switced from load to load using analog multiplexer (internal).In some cases ... Show More
BUTA_1301626
PSoC™ 5, 3 & 1
I have a rf transceiver project. I'm using a total of 2 psoc kits. I use the first on the receiver side and the second on the transmitter side.send in... Show More
GUPA_1336776
PSoC™ 5, 3 & 1
HiADC_SAR get result with 2'complement.How can i get ADC SAR result without signed.Thank'sP.G Show More
moshc_4060821
PSoC™ 5, 3 & 1
I have PSoc 5lp development kit. and I am studying segment lcd component. for that if i try to debug the example code "SegLCD_LowPowerExample" I could... Show More
Jweaver
PSoC™ 5, 3 & 1
I'm wondering why the psoc 5LP kit has two sets of dedicated I2c lines even though they are labeled I2C[0] .  Can someone please clarify-  see picture... Show More
Forum Information

PSoC™ 5, 3 & 1

The PSoC™ 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.