PSoC™ 5, 3 & 1 Forum Discussions
i want to give variable input to AND gate in cysch so that i can change that input according to my conditions programatically. how to do that?
for example:
i am using counter.
if compare gives high output then and gate should take zero as a input else AND should take one as a input.
Best Regards
Show LessHello,
I found " PSoC 3/5 Power Estimator Spreadsheet" in CYPRESS download.
www.cypress.com/file/45771/download
Is this available for PSoC5LP?
The current consumption under "T = 25 °C, VDDX = 2.7 V to 5.5 V, FCPU = 24 MHz" is typ 8.9mA.
The other condition is "Sum of digital and analog IDDD + IDDA. IDDIOX for I/Os not included.
IMO enabled, bus clock and CPU clock enabled. CPU executing complex program from flash."
On the other hand, the current consumption in the spreadsheet is 12.1mA below.
I think that this includes the current of both Vdda and Vddd. So, this current is larger than one in the datasheet.
Is this correct?
Best regards,
Yocchi
Show LessHi,
having some free days, continuing my work on an audio signal generator on a CY8CKIT-059. With help of Odissey and his components (DDS24 24-bit DDS arbitrary frequency generator component and hardware multiplier), I can output a waveform with variable amplitude. So, first many many thanks to Odissey and his valuable contributions to the community.
Now, I have some noise in output when using the headphones, but when connected to soundcard input, there's no noise. The noise sounds like some sort of ripple related to the amplitude control, but it's hard to describe. I'm not sure if it also can be some sort of overtones.
Current test setup is 1kHz sine wave, with an triangle amplitude control waveform of ~0.5Hz. Sample frequency is 512kHz. Output device is 16 Ohm headphone. Connection from two internal OpAmps (one for left & right each) to headphone is done by 100uF in series for each channel, nothing else.
To verify my output stage, I used the PSoC 5LP audio example, which makes the PSoC appear as an USB soundcard, modified the example to my output stage and played some songs. Here, the sample frequency of the device is 32kHz. Using the headphones, there's not the same noise I can hear with the PSoC generated sound. There's only some...hmm, I think it's called "pink" noise, which is what you can expect from low-cost casette playback devices from the 80's/90's So, this let me assume that my output stage is okay.
Next idea was to connect the device to the soundcard and record the input to have a test sample, showing the problem - but interestingly there's no "ripple" noise So I can't show you the problem. I've also written a small C# application, generating the same sound as described above (1kHz sine with 0.5Hz triangle amplitude) and used it with the USB soundcard application, no ripple noise, even when changing the sample rate and/or bit depth of the generated sound... I also changed the headphones, no effect.
In short:
- signal generator application & headphone: not OK
- signal generator application & soundcard: OK
- USB soundcard application & headphone: OK
So, I assume there's some sort of filtering and/or audio processing when using the soundcard, which is missing when using the headphones. How can I figure out where the error is and how to solve it?
Regards
Show LessHi all,
I am new to PSOC 5 LP. I just have the target PSOC 5 LP and not the prog kit. So I have got the MiniProg3 kit to program the PSOC 5 LP. I wanted to communicate with the PSOC using UART. I was wondering can J6 (Micro to USB) be used for UART communication? If yes please can you point to an example for the implementation of the same.
Thank you.
Show LessHow can I disable Global interrupt when I am debugging? It used to work by clicking on the lighting bolt. It is no longer working. Does anyone have a clue?
Thanks for your help!
Show LessI have an issue I am trying to track down and am wondering if anyone here has any insight. The entire chip (CY8C9540) crashes/resets when toggling certain input pins (P1_B6 and P1_B7). Every pin on that port is configured the same (pulled up) and are also used as inputs, but these two will periodically (roughly 50% of the time) reset the entire chip when pulled low. The other inputs work fine and as expected. The only thing I can think of is maybe the problem is related to these pins also sharing I2C address functionality, but pin A0 is pulled hard to ground, so they should be out of that picture. Has anyone else ran into this issue of have any ideas for me to try? Thanks.
Show LessHello @ll,
If you want to configurate, debug and test your implementation interactive, you can do this with mecrisp-stellaris, an FORTH implementation for several Cypress PSOCs.
Example:
To initiate a PWM there are several API's to do this. One API write the compare value:
To using this API you can call the API in a C-function. To modifies it on the fly you can use the configure menu from PSOC-Creator and translate and flash the whole application.
Alternative you can do following, if you have install mecrisp-stellaris:
100 PWM_1_WriteCompare1() <enter> \ 100 is put on the data stack and the API 'PWM_1_WriteCompare1()' will be calling. /!\ translating and flashing are not necessary
You can also define a word like this:
: MaxDuty1
100
PWM_1_WriteCompare1()
;
or that
: MinDuty1
0
PWM_1_WriteCompare1()
;
... MaxDuty wait MinDuty .... \ for more examples download one of following mecrisp-stellaris implementations:
As already published here, the FORTH development environment 'mecrisp-stellaris' is available for download for the following 7 Cypress PSoC's:
Board: / PSoC:
CY8CKIT-043 -> cy8c4247azi
CY8CKIT-044 -> cy8c4247azi
CY8CKIT-046 -> cy8c4248bzi
CY8CKIT-049 -> cy8c4245axi
CY8CKIT-050 -> cy8c5868axi
CY8CKIT-059 -> cy8c5888lti
FreeSoC2 -> cy8c5888axi
See: https://sourceforge.net/projects/mecrisp/files/Cypress/
If you would like to know more about FORTH, you will find the classic Starting-FORTH and Thinking-FORTH by Leo Brodie:
http://thinking-forth.sourceforge.net/
The Definition of ANS FORTH you can find here: http://lars.nocrew.org/dpans/dpans.htm
If you want to know more about Mecrisp-Stellaris you are right here:
https://www.forth-ev.de/filemgmt_data/files/4d2015-arm.pdf
When PSoC evaboard is not listed and you interest on a Forth for your board, please contact me via the e-mail address provided in README of one of the downloads to clarify the possibility of porting
Klaus
Show LessHi,
I wonder if there's a "best practice" to test self-made components. Of course, if a component works as intended for the project it's made for, this is a good result. But in my opinion this is not enough, because in the next project where the component is used there might be other circumstances. So, how do you test your components?
For example, for input signals (either hardware or API controlled), I set the input signals (in case of hardware by control register), and the component clock is controlled also by a control register, not bus clock or similar (if there are input strobes, the clock is not generated synchronously to them, but after settings them). For output signals, if there's a strobe or ready output, I use sticky status registers with the strobe/ready signal as clock.
The corresponding test firmware stimulates all "useful" (not neccessarily possible) input combinations, verifies the outputs against the expected results and outputs errors on UART. But I don't know if this is testing enough. And I've to admit that each test firmware tries to use the same approach, but I always end up with "special" code for a given component - I always feel that my test approach is not abstracted enough.
Currently, I don't use external instruments like logic analyzer or pattern generator to verify the behaviour of a component. I know there's an chapter in the component author guide about simulating components, but this is totally outside of my knowledge. So, are you testing components with external instruments or simulation?
Regards
Show LessDear Community,
here we go again.
So I manged to write a code that writes values into the flash but now I am facing a problem that looks very weird to me (bug?).
I created a variable in flash "store" (address: 0x000013d8) and intilized it with a value of 2.
Then I wrote using the EEPROM_Write(...) function a new value of 3 in the flash:
Then I tried to read this value into a uint8 variable state (address 0x1fff8168) (it does not work with state=store either):
The problem is; after the first line the state variable contains allways the intializing value (in this case 2) and not what is actually stored under the address of store (the value under the address 0x000013d8 is still the same (3)).
Show Less
Hi All,
I have seen a lot of posts about I2C transmission issues, but none that seem to help point me in the right direction.
I have an issue where every time I try to send a message to a slave that doesn't exist on the bus, the whole PSoC freezes up! I can trigger it at will and using the debugger I have found it gets stuck in the while loop on line 29 of the following chunk of generated code:
uint8 I2C_Master_MasterSendStart(uint8 slaveAddress, uint8 R_nW)
{
uint8 errStatus;errStatus = I2C_Master_MSTR_NOT_READY;
/* If IDLE, check if bus is free */
if(I2C_Master_SM_IDLE == I2C_Master_state)
{
/* If bus is free, generate Start condition */
if(I2C_Master_CHECK_BUS_FREE(I2C_Master_MCSR_REG))
{
/* Disable interrupt for manual master operation */
I2C_Master_DisableInt();/* Set address and read/write flag */
slaveAddress = (uint8) (slaveAddress << I2C_Master_SLAVE_ADDR_SHIFT);
if(0u != R_nW)
{
slaveAddress |= I2C_Master_READ_FLAG;
I2C_Master_state = I2C_Master_SM_MSTR_RD_ADDR;
}
else
{
I2C_Master_state = I2C_Master_SM_MSTR_WR_ADDR;
}/* Hardware actions: write address and generate Start */
I2C_Master_DATA_REG = slaveAddress;
I2C_Master_GENERATE_START_MANUAL;/* Wait until address is transferred */
while(I2C_Master_WAIT_BYTE_COMPLETE(I2C_Master_CSR_REG))
{
}#if(I2C_Master_MODE_MULTI_MASTER_SLAVE_ENABLED)
if(I2C_Master_CHECK_START_GEN(I2C_Master_MCSR_REG))
{
I2C_Master_CLEAR_START_GEN;/* Start condition was not generated: reset FSM to IDLE */
I2C_Master_state = I2C_Master_SM_IDLE;
errStatus = I2C_Master_MSTR_ERR_ABORT_START_GEN;
}
else
#endif /* (I2C_Master_MODE_MULTI_MASTER_SLAVE_ENABLED) */#if(I2C_Master_MODE_MULTI_MASTER_ENABLED)
if(I2C_Master_CHECK_LOST_ARB(I2C_Master_CSR_REG))
{
I2C_Master_BUS_RELEASE_MANUAL;/* Master lost arbitrage: reset FSM to IDLE */
I2C_Master_state = I2C_Master_SM_IDLE;
errStatus = I2C_Master_MSTR_ERR_ARB_LOST;
}
else
#endif /* (I2C_Master_MODE_MULTI_MASTER_ENABLED) */if(I2C_Master_CHECK_ADDR_NAK(I2C_Master_CSR_REG))
{
/* Address has been NACKed: reset FSM to IDLE */
I2C_Master_state = I2C_Master_SM_IDLE;
errStatus = I2C_Master_MSTR_ERR_LB_NAK;
}
else
{
/* Start was sent without errors */
errStatus = I2C_Master_MSTR_NO_ERROR;
}
}
else
{
errStatus = I2C_Master_MSTR_BUS_BUSY;
}
}return(errStatus);
}
Now I know for sure that if the I2C master tries to communicate with a slave that isn't present, it shouldn't cause the bus to fail. I have NO idea why it is and it's causing me serious problems because of the intended application.
Below is a copy of my I2C code:
#include "project.h"
#include "I2C.h"void I2C_Delay();
void I2C_Reset();uint8 I2C_Start()
{
I2C_Master_Start();
return I2C_SUCCESS;
}void Clear_Read_Buff(uint8* data, uint8 data_length)
{
for(uint8 i = 0; i < data_length; i++)
{
data = 0;
}
}uint8 I2C_Master_Write_Data(uint8 slave_address, uint8* data, uint8 data_length)
{
uint8 status = 0;
status = I2C_Master_MasterSendStart(slave_address, I2C_Master_WRITE_XFER_MODE);
if(status == I2C_Master_MSTR_NO_ERROR)
{
for(uint8 i = 0; i < data_length; i++)
{
status = I2C_Master_MasterWriteByte(data);
if(status != I2C_Master_MSTR_NO_ERROR)
{
I2C_Master_MasterSendStop();
I2C_Delay();
I2C_Reset();
return I2C_FAILURE;
}
}
}
else
{
I2C_Master_MasterSendStop();
I2C_Delay();
I2C_Reset();
return I2C_FAILURE;
}
I2C_Master_MasterSendStop();
I2C_Delay();
return I2C_SUCCESS;
}uint8 I2C_Master_Read_Data(uint8 slave_address, uint8 mem_loc, uint8* data_buf, uint8 data_length)
{
uint8 status = 0;
status = I2C_Master_MasterSendStart(slave_address, I2C_Master_WRITE_XFER_MODE);
if(status == I2C_Master_MSTR_NO_ERROR)
{
status = I2C_Master_MasterWriteByte(mem_loc);
if (status != I2C_Master_MSTR_NO_ERROR)
{
I2C_Master_MasterSendStop();
I2C_Delay();
I2C_Reset();
return I2C_FAILURE;
}
}
else
{
I2C_Master_MasterSendStop();
I2C_Delay();
I2C_Reset();
return I2C_FAILURE;
}
status = I2C_Master_MasterSendRestart(slave_address, I2C_Master_READ_XFER_MODE);
if(status == I2C_Master_MSTR_NO_ERROR)
{
for(uint8 i = 0; i < data_length - 1; i++)
{
data_buf = I2C_Master_MasterReadByte(I2C_Master_ACK_DATA);
}
data_buf[data_length - 1] = I2C_Master_MasterReadByte(I2C_Master_NAK_DATA);
}
else
{
I2C_Master_MasterSendStop();
I2C_Delay();
I2C_Reset();
return I2C_FAILURE;
}
I2C_Master_MasterSendStop();
I2C_Delay();
return I2C_SUCCESS;
}/* I2C Read with a 16 Byte Memory Location */
uint8 I2C_Master_Read_Data16(uint8 slave_address, uint16 mem_loc, uint8* data_buf, uint8 data_length)
{
uint8 status = 0;
uint8 mem_loc_h = (mem_loc & 0xFF00) >> 8;
uint8 mem_loc_l = (mem_loc & 0x00FF);
status = I2C_Master_MasterSendStart(slave_address, I2C_Master_WRITE_XFER_MODE);
if(status == I2C_Master_MSTR_NO_ERROR)
{
status = I2C_Master_MasterWriteByte(mem_loc_h);
if(status == I2C_Master_MSTR_NO_ERROR)
{
status = I2C_Master_MasterWriteByte(mem_loc_l);
if (status != I2C_Master_MSTR_NO_ERROR)
{
I2C_Master_MasterSendStop();
I2C_Delay();
I2C_Reset();
return I2C_FAILURE;
}
}
}
else
{
I2C_Master_MasterSendStop();
I2C_Delay();
I2C_Reset();
return I2C_FAILURE;
}
status = I2C_Master_MasterSendRestart(slave_address, I2C_Master_READ_XFER_MODE);
if(status == I2C_Master_MSTR_NO_ERROR)
{
for(uint8 i = 0; i < data_length - 1; i++)
{
data_buf = I2C_Master_MasterReadByte(I2C_Master_ACK_DATA);
}
data_buf[data_length - 1] = I2C_Master_MasterReadByte(I2C_Master_NAK_DATA);
}
else
{
I2C_Master_MasterSendStop();
I2C_Delay();
I2C_Reset();
return I2C_FAILURE;
}
I2C_Master_MasterSendStop();
I2C_Delay();
return I2C_SUCCESS;
}uint8 I2C_Master_Read_Byte(uint8 slave_address, uint8* result)
{
uint8 status = 0;status = I2C_Master_MasterSendStart(slave_address, I2C_Master_READ_XFER_MODE);
if(status == I2C_Master_MSTR_NO_ERROR)
{
*result = I2C_Master_MasterReadByte(I2C_Master_ACK_DATA);
}
else
{
I2C_Master_MasterSendStop();
I2C_Delay();
I2C_Reset();
return I2C_FAILURE;
}
I2C_Master_MasterSendStop();
I2C_Delay();
return I2C_SUCCESS;
}void I2C_Delay()
{
CyDelay(I2C_DELAY_MS);
}void I2C_Reset()
{
I2C_Reset_Reg_Write(0b1);
I2C_Master_Stop();
I2C_Master_Start();
// Indicator_LED_OUT_Write(0x00);
// CyDelay(50);
// Indicator_LED_OUT_Write(0x01);
// CyDelay(50);
// Indicator_LED_OUT_Write(0x00);
// CyDelay(50);
// Indicator_LED_OUT_Write(0x01);
// CyDelay(50);
// Indicator_LED_OUT_Write(0x00);
}
Any and all help is appreciated! I have no idea what I am doing wrong.
Show Less