PSoC™ 5, 3 & 1 Forum Discussions

Hi there

I'm trying to found a way to set the 3 DM bits of each pin belonging to 8 pin port 4 (in this case)  to set

all of them except one to HI- Z.

I have looked at TRM and CY boot component but according to my understanding that's is not possible with few line of code.

Any Help ?

I am using the CY8C20234 CPU. Previously, I used assembly language to set Port 1 to STRONG with voltage to 2.4 VDC. The initial value was set in the PSOC Designer Pinout menu to 1.

or   F,           %00010000

or   REG[IO_CFG], %00110010

and  F,           %11101111

This works correctly, putting out 2.4VDC on pin 1_2.

I have tried this in C, but the voltage on this pin end's up being 0VDC.

asm("or  F,         %00010000");

asm("or  REG[0xDC], %00110010");

asm("and F,         %11101111");

I think it might have to do with the register address which I borrowed from the assembly project's hex output. Though either way I am sure there is a better way to do this in C. What is the best way to do accomplish this in C?

On the cy8c20234 cpu, I have created two projects on PSOC Designer 5.4, one in Assembly, the other in C. I can get the internal timer interrupt to work correctly in assembly, but it does not seem to work in C. This CPU must also work with I2C. Those are the only two "features" I need from this CPU.

What could I be doing wrong?

Hi,everyone.

     CapSense can be CSA or CSD. From Datasheet, I found many cypress SOCs has the Capsense with CSD in it.

     Then which SOC was embeded witch CSA?

      And what is the CSD advantage over CSA?

     is there any toolbox for such SOCs with CSA to tune all parameters? for example, an guideline file,"CY8CMBR2016 CapSense MBR Design Toolbox for 16 buttons". but it is based on CSD.

Hello everyone!

I'm trying to transmit two audio signals using two PSOC 5LP cards, the first one is going to be an input card and the second is going to be an output card. I chose to use a Delta Sigma ADC on a multi Sample mode with a sampling frequency of 44 kHz and a resolution of 12 bits (I'm trying to get closer to the HIFI norm). I chose an Analog Mux to multiplex my two signals.

On the other card, a DVDAC of 12 bits and an Amux. The transmision is done by UARTS working in a speed of 921600 bps.

Since the UARTs can only send 8 bits each time, I divided the ADC output on two parts and added two bits to each one to adress the channel and to know if it is a MSByte or an LSByte. We only use 12 bits out of 16 bits = (6+2) bits + (6+2) bits which is the size of the ADC Output and the DAC Input.

The following pieces of code show the used protocole.

On the input card:

On the output card:

My question is as follows: Is this the correct way of using an Analog multiplexer? Why is it that I get a noisy signal out of the second card which does not change with the frequency of the sinewave on the input?

I know I'm asking a lot but I really need help with this project in order to validate my semester. Thank you!

I have been trying to use one del-Sig ADC to sample several sources.... And I ran into some problems:

I was using EOC bit feeding a Status Register to let me know when the ADC is done a conversion (with anticipation of future expansion for UDB functionality instead of the status register). On single channel, this seemed to work. However, when using more than one channel, I didn't seem to get any meaningful results. In one case, I got zeros. In another case, it seemed that it wasn't actually switching the source properly, despite the MUX being independent to the ADC.  However, I just learned that the EOC bit that I had feeding a status register doesn't work, as per https://community.cypress.com/thread/19402?q=delsig%20mux .Now that I'm using "ADC_DelSig_IsEndConversion(ADC_DelSig_WAIT_FOR_RESULT)", my ADC seems to be working correctly. But... I read that "

The DSI routable signal does not work.

...

FIX STATUS
Silicon revision fix available in ES2.

"

...so did this never get fixed?

I also noticed in an example from Psoc a different order of operations than I preform...

My Order of Operations:

1. Select Mux

2. Start Convert

3. Wait until finished

4. Get result

5. Stop Convert

Cypress Psoc Example Order of Operations:

1. Select Mux

2. Start Convert

3. Wait until finished

5. Stop Convert

4. Get Result

Is there any particular reason they stop the conversion before getting the result? I was under the impression that stopping the conversion flushes the ADC, which is why I didn't/don't do it that way, as I assumed that the ADC result may get recycled. However, it seems just fine in the example? So... If I did it my way, is there anything wrong with that? Could the result get overwritten by a new result, if I don't grab it fast enough? Why doesn't their result get overwritten by the stopconvert? What am I missing here?

Hi,everyone.

     I have some questions about Cy3280-BK1,which contains CY3280-20x34 and CY3280-21x34 Universal CapSense Controller boards.

     Now I use bridge control panel to read touch data from CY3280-21x34 board and display them. but data and chart are totally different from expectation.

     In the following chart and table,raw counts  sharply reduce from 62730 to 10 instead of increasing when finger touchs the sensor.And the touch data is 10 ,stays the same . why does it work in this way?

     According to CSD theory, Cf+Cp will lead to an bigger raw counts.

     Question2: CY3280-20x34 uses CSA while CY3280-21x34 uses CSD. which one  is better,CSD or CSA ? what are the advantages and disadvantages of each?

I'm using the CY8C24894-24LTXI on a board mainly as a simple USB interface to the outside world (which can be both windows or embedded hosts). The PSoC1 is always a device. I recently have enumeration problems that pop up. In looking closer at the PSoC1 side, the D+ pullup measures much higher than the spec 1.5K, closer to 2k. This appears to add to the startup issues. There's not much in the Developer's USB wizard that I can see would bias the D+ pullup value.

Has anyone seen this issue, or any tips on what we might be doing on startup that would effect the D+ pullup? This is not a new board (like over 10 years), so nothing has changed in years.

Thanks - Steve