I tried to implement the hibernate example from this project on my board and it gets stuck in hibernate mode. So I took out the CY8CKIT-059 and modified my code example a bit to fit this board and it still gets stuck in hibernate mode, well sort of. I think it is accepting the GPIO interrupt partially since the current draw increases after the button press, but it does not execute any of the code after the CyPmHibernate(); CyPmRestoreClocks();. The code is slightly modified from the by example by blinking the LED so I can see where in the code we are without debugging. I have attached the project.
The CE95346 - Power Management and Hibernate with PSoC 3/5LP example does work maybe because of the custom ISR?
Any Ideas? (could I have some system setting wrong?) I haven't found any note to a similar problem.
Here is the Hibernate section of the code:
case HIBERNATE : /* 0x41 - Hibernate - PICU */
{
/* Display mode and set LCD pins for low-power. */
LCD_Position(1,0);
LCD_PrintString("Hibernate ");
LED_S_Write(LED_OFF);
/* Start the button interrupt. */
isr_ButtonPress_Start();
SleepComponents();
LED_S_Write(LED_OFF);
CyDelay(1000u);
LED_S_Write(LED_ON); //blink the LED so I know where I am in the code
CyDelay(1000u);
LED_S_Write(LED_OFF);
CyDelay(1000u);
LED_S_Write(LED_ON);
CyDelay(1000u);
LED_S_Write(LED_OFF);
/* Save clocks and enter low power. */
CyPmSaveClocks();
CyPmHibernate();
/* The PSoC wakes up here. Restore everything and clear PICU interrupt. */
CyPmRestoreClocks();
LED_S_Write(LED_ON); //Status LEDs so I know where I am in the code
CyDelay(1000u);
LED_S_Write(LED_OFF);
CyDelay(1000u);
LED_S_Write(LED_ON);
WakeComponents();
/* Stop the button interrupt. */
isr_ButtonPress_Stop();
Button_ClearInterrupt();
break;
}
I am working on a Flash Write routine which is part of a boot loader for the CY8C27243. I am using Application AN2100 as a starting point. I have all aspects of the bootloader working except for Flash Write. After many days of debugging I have narrowed it down to the Supervisor ROM Flash Write sequence which uses the M8C SSC instruction.
Here is a simplified sequence used to access a supervisor ROM routine as found in FLASHAPI.asm which is part of AN2100. This is part of the temperature table access routine and is a very simple use of the supervisor ROM and should work.
push A ; save the State variable
push X
mov X, SP ; copy SP into X
mov A, X ; mov to A
add A, 3 ; create 3 byte stack frame
mov [0xF9], A ; save stack frame for supervisory code
mov [0xF8], 0x3A ; load the supervisory code for flash operations
mov A, 6 ; load A with FLASH_TEMP_TABLE_LOOKUP rom code
SSC ; SSC call the supervisory code
pop X
Code execution does not return after the SSC instruction. I am assuming it is halting for some reason.
I have double checked all of the parameters and can't figure out what I am doing wrong. Can SSC only be called when the M8C is in a certain mode ? I have been able to read Flash successfully since that routine uses the absolute ROM read instruction ROMX which avoids an SCC. I wish there was such an easy way to do a write.
I have been working on this bootloader for nearly a month now and need to finish this before new product release.
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Hi there,
I have a question regarding the code checksum on a PSoC5LP part (specifically CY8C5667AXI-LP040).
I have a request on a project to provide the checksum of code over a serial interface. Is there a known good way during runtime to either read or calculate the checksum of the entire codespace of the PSoC? Perhaps even an API function I'm not aware of?
Thanks for the help!
Show LessA PSoC5LP controls power supply sequencing for an FPGA. The PSoc5LP measures and reports current and voltage on the FPGA's power rails as well as FPGA die temperature to a host system via a USB to UART bridge.
The PSoC5LP's USB interface is permanently connected to a CY7C65642 embedded USB hub. No USB cables are ever inserted or removed. However, aggressive power management is being done. Power to most of the system is removed unless the system is operational. The embedded USB hub will be powered off when the system is idle.
The PSoC5LP is powered from +3.3V continuously from an "always on" power supply. The PSoC5LP is performs power management by turning power off and on to the rest of the system. The PSoC5LP will power the entire system up from idle after a period of time has elapsed or by an external wake up signal.
Questions:
1. What is the proper way to connect power and USB signals to the PSoC5LP so that a "self powered" USB interface is created? Many other MCUs have a "VBUS" input to monitor USB bus voltage. I don't see that on the PSoC5LP.
2. Should the PSoC5LP's USB interface be "re-initialized" after power to the embedded USB hub is applied to mimic the insertion of a USB cable? If so, how?
Thanks for your help dealing with these USB "corner cases"!
Wayne
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Does this device have input voltage ripple or spike regulations?
Ripple will occur up to 130mVp-p at 5V in low temperature conditions. LVD is set to 4.81V(Typ), but it has not been reset. (VM[2: 0] = 111b)
Thanks,
Tetsuo
I would like to use a PSoCLP5 as a "power manager" for a large Xilinx FPGA. The PSoC5LP controls the sequencing of power supplies to the FPGA, monitors current and output voltage of every FPGA supply rail, temperature, etc.
All of these measurements are reported over I2C to the FPGA and via a USB to UART bridge (implemented in the PSoC5LP) to a host system. All of these requirements make the PSoC5LP a very good solution.
The PSoC5LP is powered continuously from a switching regulator that runs slightly above the dropout voltage of two LDOs. One of the LDOs produces +3.3V for most of the I/O and VDDA. VDDA is powered though a LC filter. The other LDO produces 1.8V for producing one of the I/O banks VDD.
Driving an unpowered FPGA will forward bias the ESD diodes on its inputs causing a voltage to appear on its power supply rails. Unless the generated voltage is kept below 2.5V when the FPGA is not powered, the Xilinx device may be damaged. One robust solution is to run the I/O between the PSoC5LP and the FPGA at 1.8V.
Here are a few questions:
1. Are there any power sequencing requirements among the PSOC5LP's power supply rails?
2. If an I/O bank is not in use is it safe to remove power for that bank? Will the rest of the PSoC5LP I/O on other banks continue to function normally?
Thanks for your help,
Wayne
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Hello, Can anyone help me convert this ancient 8bit pic code to run on the PSoC 5?, Ideally I would like to use flash instead of EEprom, I do not know enough about the Pic code structure,
start-up the very first time, RA4 (port A.4) is held high and
; thereby initializing the rec, pulse, wait time in the EE plume.
; If RA4 is low during takeoff, the EE plume is read instead.
; Note that RA4 has dual function as it at high (after
; start can be used (via RA0, RA1) to adjust the number of pulses
; REMEMBER to set low again before the next ON / OFF.
;
;
;
; LIST P = 16C84, F = INHX8M
include "p16c84.inc";
; uP PIC16C84 include module ver. 1.00
; ----------------- DIV -----------------
ORG 0; Dummy origin
goto INIT; ; jump to INIT
; -------------- ------------- constants
d1 equ. 20; pulse time in us
d2 equ. 10; (wait before rec.) wait for response in us
d3 equ .5; receive in ms
d4 equ .40; (ms wait before next) wait ms before the next pulse
delay equ .6; ; delay to 1 ms hours
loop equ 0Ch; RAM 0C
xus equ 10h; RAM 10
xms equ 11h; RAM 11
pulse_time equ 15h; RAM 15
w_b_r equ 16h; RAM 16
rec_time equ 17h; RAM 17
w_b_n equ 18h; RAM 18
; RAM 11; is used by x ms hours
; RAM 12.13; used by us hours
; RAM 14; 8 flags, F0..F7
; RAM 15; pulse_time
; RAM 16; w_b_r
; RAM 17; rec_time
; RAM 18; w_b_n
;
; EEADR 00; set to 0 at startup
; ---------------- TIMER ------------------
wait_1us; ; ca 1us wait
nop;
return
wait_xus; wait x microsec.
J4
call wait_1us
decfsz xus, 1; T'l xus-1
goto J4
return
wait_1ms; ; 1 ms hours
movlw .5; number of passes for 1 ms
movwf 13; move w to RAM 13
J2 movlw delay; ; w = delay (correction)
movwf 12; move w to RAM 12
J1 decfsz 12.1; Tl RAM12-1 or later
goto J1; repeat
decfsz 13; T'l RAM13-1 or end
goto J2; repeat
return
wait_xms; Wait x milliseconds
J3 call wait_1ms
decfsz xms, 1; T xl-1
goto J3
return
; ----------- EEPROM MODULE FOR PIC16C84
; Rev 1.00
; 27th / 07-95
; note: use timer
wadr equ 2Fh; address in RAM 2F
value equ 2Eh; Data in RAM 2E
WR_EEPROM; write EEPROM (data in RAM 2E + adr in RAM 2E)
movf wadr, W; w = ADR
movwf EEADR; EEADR = w
movf value, W; w = data
movwf EEDATA; EEDATA = w
; --- write sequnce
bsf STATUS, RP0; EEPROM write enable
bcf INTCON, GIE; disable interupts
movlw 0x55; W = 55H
movwf EECON2; EECON2 = w
movlw 0xAA; w = Oh
movwf EECON2; EECON2 = w
bsf EECON1, WR; EECON1 = write
movlw .100; load time writing
movwf xms; move w to xms
call wait_xms; wait in ms
; --- end
; return
RD_EEPROM; should be in RAM 2F
movf wadr, W; data is delivered in RAM 2E
movwf EEADR; EEADR = w (adr)
bsf STATUS, RP0; bank 1
bsf EECON1, RD; set RD bit (self extinguishes)
bcf STATUS, RP0; bank 0
movf EEDATA, W; w = data
movwf value; data = w
; --- end
return
; -------------- END EEPROM MODULE
; ------------ DATA CHANGES -----------
Update
btfsc 5.4; first check bit 4
goto heart rate, adjust number of pulses
btfsc 5.0; If bit 0 is set
incf rec_time, 1; "step up" rec. hour + 1
btfsc 5.1; If bit 1 is set
decfsz rec_time, 1; "step down" rec. hour - 1
btfsc 5.2; If bit 2 is set
incf w_b_r, 1; "step up" wait before rec + 1
btfsc 5.3; If bit 3 is set
decfsz w_b_r, 1; "step down" wait before - 1
goto end, otherwise end
if 5.4
pulse just
btfsc 5.0; If bits 0 and 4 are set
incf pulse_time, 1; "step up" pulse + 1
btfsc 5.1; If bits 1 and 4 are set
decfsz pulse_time, 1; "step down" pulse - 1
GOTO end, jump to end
end
set up address + data for EEPROM change
save number of pulses
movf pulse_time, W; move to W
movwf value; value = rec_time
movwf wadr; set address
movlw 01h; to 01 hex in EE
CALL WR_EEPROM; write in EE
save wait time before receiving
movf w_b_r, W; move to W
movwf value; value = rec_time
movwf wadr; set address
movlw 02h; to 02 hex in EE
CALL WR_EEPROM; write in EE
save recipient time
movf rec_time, W; move to W
movwf value; value = rec_time
movwf wadr; set address
movlw 03h; to 03 hex in EE
CALL WR_EEPROM; write in EE
; hours start
movlw 04h
movwf loop; put 2 in RAM 0C
T_1
wait 1 sec
movlw .255; ; 1/4 sec load
movwf xms; move w to xms
call wait_xms; wait for w_b_n ms
decfsz walk, 1; walk
goto T_1
;than
return
DEFAULT
movlw d1; w = delay 1
movwf puls_time; Pulse time = w
movwf d2; w = delay 2
movwf w_b_r; wait before receive
movwf value; data (EE) = w
movlw d3; w = delay 3
movwf rec_time; record time
movwf value; data (EE) = w
movlw d4; w = delay 4
movwf w_b_n; wait (deleted later)
CALL Update; write to EE
goto MAIN
; -------------- INIT -------------------
INIT
output init
movlw B'11111111 '; set w = 0D
movwf PORTB; move w to port B
movlw B'00000000 '; set w = 00
tris PORTB; look out all I / O direction
input init
movlw B'11111 '; set bit 0..4 for input
tris PORTA; set port A
; init RAM / EEPROM
btfsc PORTA, 4; If port A bit 0 read by default
goto DEFAULT
movlw 01h; ; W = 01h
movwf wadr; adr = w
call RD_EEPROM; Read EE
movf value, W; w = EEPROM data
movwf pulse_time; pulse = w
movlw 02h; ; W = 02h
movwf wadr; adr = w
call RD_EEPROM; Read EE
movf value, W; w = EEPROM data
movwf w_b_r; wait before receive
movlw 03h; ; W = 03h
movwf wadr; adr = w
call RD_EEPROM; Read EE
movf value, W; w = EEPROM data
movwf rec_time; record time
movlw d4; w = d4 (deleted later)
movwf w_b_n; wait (deleted later)
goto MAIN; HOP TO THE HEADLY
;---------------- PULSE -------------------
pulse
bcf PORTB, 0; bit 3 = 0 (output)
movf pulse_time, 0; move pulse_time to w
movwf xus; move time to RAM11
call wait_xus; wait for x us
bsf PORTB, 0
return
;--------------- RECEIVE ------------------
receiver
bcf PORTB, 3; bit 0 = 0 (receiver opens)
movf rec_time, 0; move time in us to w
movwf xus; move time in RAM16
call wait_xus; wait for x us
bsf PORTB, 3; close receiver
return
; ----------------- MAIN --------------
MAIN
; Pulse
call pulse; call pulse routine
; Wait
movf w_b_r, W; load w with wait
movwf xus; move w to xus
call wait_xus; wait in w_b_r us
; receive
call receiver; open receiver
; Wait
movf w_b_n, W; load time to next pulse
movwf xms; move w to xms
call wait_xms; wait for w_b_n ms
; read input
btfsc 5.0; if up active
call update; call update
btfsc 5.1; if down active
call update; call update
btfsc 5.2; if up active
call update; call update
btfsc 5.3; if down active
call update; call update
; repeat
goto MAIN
than
; END
when i read the AN2163 ,
The document does not clearly mention the physical connection of 18b20
My connection method is shown in the figure,pin16,pin17
Connect them together, and then connect to the 18b20 signal line,Is this right?
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Hello PSoC developers!
I am using PSoC 5LP (devkit) and I would like to implement a proximity sensor that returns '1' when a finger threshold is reached, e.g. signal value of 100.
This value 100, which is derived from the raw signal and the baseline value, is stored in sensorSignal array.
I have noticed that the sensorSignal is used in CapSense_CheckIsSensorActive(uint8 sensor) function, which I use to check if the finger threshold has been reached. During debugging I have noticed that sensorSignal is always 0, even though the raw data and the baseline are correctly measured and updated.
My questions are:
How does the CapSense_CheckIsSensorActive ever return '1' when the sensorSignal only gets updated when a baseline is updated (accroding to datasheet of CapSense component)?
In general, how does one obtain a flag ('0' or '1') when the finger threshold has been reached?
Best regards,
Matija.
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