PSoC™ 5, 3 & 1 Forum Discussions
I got trouble to do List on BCP using my PC but it works on other PC. How to fix this?
for the programming and debugging purpose i want to use JTAG in this CY8C5467LTI-LP003 chip, now my questions are,
1) if i power up the board with 5V , will the JTAG pins logic levels are nearly 5V? or it can be 3.3v?
2) can i use "J-LINK EDU MINI" as programmer for this chip as i already own it, but the datasheet of j-link edu mini states that to use it with 3.3v and as i already stated that my CY8C5467LTI-LP003 will be powered up with 5V.
3) is there any JTAG programmer for this CY8C5467LTI-LP003 chip from cypress? will it work with my chip if i powered up my chip with 5V?
4) "CY8CKIT-059" this have "KitProg" biult on the board which can be separated from the main board , my question is that , is that possible to use this KitProg to debug/program any "CY8C5467LTI-LP003" chip? is that KitProg having JTAG pins? or just SWD?
Show Less"LMT70" this sensor outputs ADC temperature data, for the cypress "CY8C5467LTI-LP003 " this chip which ADC i should go for, SAR or delta? connection diagram will be more appreciable with some example design screenshot in PSoC creator.
Show LessI've developed code that uses the recommended while((USBUART_CDCIsReady()) == 0){} before sending new data to the host.
All is working great if the host is connected and the port is open. As soon as a close the host port, eventually the PSoC app code hangs on the while() statement shown above.
Is there a proper way to detect if the port is open to accept new data?
Len
Show LessHi,
is there a method of storing different UDB builds in PSoC 5LP (or PSoC 4) Flash and RAM and selecting one of them for one task and another for other task ?
The pins and resources accessed by UDB blocks will be the same just UDB schematics (or Verilog code) varies ?
Thanks.
Show LessWhen the device is powered up (PSoC 5 in this case) windows adds it to the device list in device manager. The vendor id and product id is the default.
Once the custom driver for the device is loaded, which includes the .inf file, it is then reported in device manager with the custom VID/PID.
Is there a way to embed the a custom VID/PID in the device so that it always shows the custom VID/PID without having to install the driver/inf file first?
Show LessHello,
Enabling external XTAL on PSoC3 adds a loop that checks the xerr bit of the register (FASTCLK_XMHZ_CSR) in the ClockSetup() function of the boot procedure.
This loop period is 130ms by default.
ClockSetup () checks bit7 (xerr) of CYREG_FASTCLK_XMHZ_CSR every 10us. but when is this register actually updated?
Some ICs exit this loop and others stay 130ms within error.
Show LessHello,
I'm considering using the PSOC5LP in my design.
One of the requirements is clock synchronization, i.e. I need to apply an external clock into the PSOC (and other devices) from external external PLL device.
I saw that there is an option to apply an external XTAL ('MHzECO').
Is it posiible to apply just a Clock signal (say LVDS/LVPECL logic level), without using a XTAL?
Thanks!
Show LessHello,
Until the IMO setting is completed in ClockSetup(), the frequency of the IMO is not adjusted by Trim.
The oscillation accuracy of IMO after Trim can be confirmed with the data sheet specifications (± 2% @ 3MHz).
What is the oscillation accuracy of IMO before Trim?
Show LessI am planning to use PSoC 3 in my new design. Had been using it three to four years back. Just wanted to know whether the Keil compiler is still freely provided along with PSoC creator without any limitation to have production releases.
Show Less