PSoC™ 5, 3 & 1 Forum Discussions
Hi, I am currently using the CY8C5888AXI-LP096 for a project. I have connected the XRES(Pin 15) line to a port for programming so that I can support programming in the field.
During testing, i found that the line can glitch, which seems to cause instability in my design.
Is there a way to disable the XRES line during normal operation?
I was reading some documentation and it mentioned that in the NV Latch register I could toggle the XRES to a GPIO pin. But Looking through my code base, I can't seem to access the NV Latch register. How do I access the NV Latch register?
I have tried using the optional XRES setting, but that changes pin#22 to the XRES line, and what i am looking for is how can I disable the XRES on pin #15.
If there is no way to disable (pin#15 XRES), what would you recommend to do to stabilize my system, but still have the capability to program the MCU?
Any help would be appreciated.
Thank you.
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What are these memories(marked red) used for in cyfitter_cfg.c? And how to decide their size?
static const cfg_memset_t CYCODE cfg_memset_list[] = {
/* address, size */
{(void CYFAR *)(CYREG_PRT0_DR), 16u},
{(void CYFAR *)(CYREG_PRT3_DR), 64u},
{(void CYFAR *)(CYREG_PRT15_DR), 16u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},
};
I even cannot find defnition of below memories(marked red) in the datasheet.
CYCONFIGCPY((void CYFAR *)(CYREG_PRT12_DR), (const void CYFAR *)(BS_IOPINS0_7_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT1_DM0), (const void CYFAR *)(BS_IOPINS0_1_VAL), 8u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DM0), (const void CYFAR *)(BS_IOPINS0_2_VAL), 8u);
I've got a project where the customer wants to use a long (5M+) USB cable to connect our PSoC5LP-based USB HID. The issue being that USB Full-Speed max cable length is 3M.
Can I do anything to reduce the PSoC5LP to a Low-Speed device rather than Full-Speed to meet this requirement? Would the host perhaps automatically switch to LS if it can't communicate over FS?
Would there be other concerns regarding speed at that point? The PSoC USBFS component is configured as a composite Mouse+Keyboard device, 2 Endpoints at 8 bytes each, which I think should be OK?
This project also has the PSoC USB device being sent out to the customer through an integrated USB hub, which may negate the issue?
Hi, Can a project data sheet be customized in PSoC Creator 4.4
Hi,
I am working on a multiple microcontroller based project in which I have two PSoC5 microcontrollers. Currently when a WDT timeout occurs in one of the microcontroller, reset occurs only for that chip. I need to perform a system level (both the microcontrollers) need to be reset when a WDT time out occurs in either of the microcontrollers.
I came across various posts in which it mentions that if the value of CyResetStatus variable is read before bootloader exexcutes the application code this can be read. But all the time I am only getting the value of CyResetStatus as 0X80 or 0XA0.
Is there a way to read the reason for reset and save the status into the internal EEPROM location.
Can someone help me in addressing the issue?
Thanks in advance.
Show LessHi There !
I have some issues to implement "double sqrt (double ) " in code.
My code include math.h but the buildin give me the attached info.
Any suggestion?
Thanks
Show LessI know this is old news, but I have a CY90F568PMC-GE1 (84509983001) in Cypress that is now EOL,
There seems to be a similar model number, CY90F568PMCR-GE1, but it is not listed in the datasheet.
Is there any data or information that shows the difference between the CY90F568PMCR-GE1 with and without the "R"?
How reliable are the example verilog models of the UDB datapaths? I've been using them to simulate and verify my UDBs before implementing code, and have been mostly successful until now.
In c:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\sim\presynth\vlg\cy_psoc3_dp.v there is the following verilog which describes the synchronization of the FIFO block status signals:
// Select extra synchronization of the FIFO status
reg fifo0_blk_extra;
wire fifo0_async_mux;
reg fifo0_add_sync;
always @(posedge read_clk_0 or posedge reset)
begin
if (reset)
begin
fifo0_blk_extra <= 0;
fifo0_add_sync <= 0;
end
else
begin
fifo0_blk_extra <= fifo0_blk_stat;
fifo0_add_sync <= fifo0_async_mux;
end
end
...
assign fifo0_async_mux = (scr8[`SC_FIFO_TYPE] == `SC_FIFO__SYNC) ?
fifo0_blk_stat : fifo0_blk_extra;
...
wire f0_blk_mux = (scr8[`SC_FIFO_SYNC] == `SC_FIFO_SYNC__ADD) ?
fifo0_add_sync : fifo0_async_mux;
The config bit `SC_FIFO_TYPE can be either `SC_FIFO__SYNC or `SC_FIFO_ASYNC. So the second last assignment appears to be wrong: if 'SC_FIFO_TYPE is 'SC_FIFO__SYNC then fifo0_async_mux should get fif0_blk_extra not fifo0_blk_stat. It looks like this expression is reversed. Does this accurately describe the hardware or is the model wrong?
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How is the external strobe feature used on a VDAC? Does it use the rising edge? I do not see it specified.
Hi, I am having an issue with CY8C5888LTI-LP09. I bought the chip for school but using the psoc creator I cant detect the board. The board is flashing blue but thats it. The rest of the LED are not on and when I select a target to download my program to the board does not appear as an option.
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