PSoC™ 5, 3 & 1 Forum Discussions

Hi,I am use SPI component on psoc5 series CY8C5888LTI Prototype kit in master mode and SPI mode_1 to communicate with AFE4400(TI company)(AFE4400 spi sclk is 8MHz).I use SPI component with in psoc creator that attach. But the problem is spi data write function in output.when i am select 8Mhz on sclk it is not create true sclk on output in data write but when i select low sclk clock like 250k or 800k or other below 1MHz it is worked well.I need 8Mhz on sclk so I do not know what is mistake exactly?

Why SPI component does not work on 8Mhz sclk?(Cypress datasheet say SPI can work up to 18MHz sclk)

Below is picture out put on oscilloscope. https://snaptube.cam/ https://9apps.cam/

PLL clock is select on 64Mhz.

I choose Enable high speed on spi component but it not difference on my problem in output.

Is there any body to help me and say me how can I solve it?

Here is the output signal show on oscilloscope that show spi component does not work correctly on 8Mhz sclk.(first is on 250KHz and second picture is on 8MHz)

please regurd me how can solve this problem with spi component?

Thanks for attention...

Hi Team,

I got CY8CKIT-050 5LP DEVELOPMENT KIT to work. Not sure how can i start. I am a c# developer. Can anyone suggest how can i create a sample application and implement this kit to the application.

BUENAS NOCHES,

TENGO UN SENSOR QUE ENTREGA SEÑALES EN MICRO VOLTIOS, PUEDO TRABAJAR CON ESTE VOLTAJE O REQUIERO AMPLIFICAR LA SEÑAL PRIMERO? CON MI Psoc  5lp.

What is the advantage of using Control Register to control a pin High / LOW state instead of simply Pin_Write ? (PSoC 5lp)

Thanks !

Peter

Hello there,

I would like to know is there a way to use serial type of memory with PSoC5 MCU's EMIF component. In one of my earlier posts I managed to run LVGL GUI on PSoC5 platform, so now I would like to use external RAM for display buffer as it is supported by LVGL. By reading a datasheet for EMIF I concluded that it's intended to be used with memories that use some sort of parallel interface. If that is the case, is there a way to use serial RAM with PSoC5 as a graphics buffer or is that only possible on PSoC6 series of MCU's with SMIF component?

Just to mention that I have no experience with EMIF or external memories so any help would be nice, and I'm sorry if my post is a bit of a mess.

Hi,I am use SPI component on psoc5 series CY8C5888LTI Prototype kit in master mode and SPI mode_1 to communicate with AFE4400(TI company)(AFE4400 spi sclk is 8MHz).I use SPI component with in psoc creator that attach. But the problem is spi data write function in output.when i am select 8Mhz on sclk it is not create true sclk on output in data write but when i select low sclk clock like 250k or 800k or other below 1MHz it is worked well.I need 8Mhz on sclk so I do not know what is mistake exactly?

Why SPI component does not work on 8Mhz sclk?(Cypress datasheet say SPI can work up to 18MHz sclk)

Below is picture out put on oscilloscope.

PLL clock is select on 64Mhz.

I choose Enable high speed on spi component but it not difference on my problem in output.

Is there any body to help me and say me how can I solve it?

Here is the output signal show on oscilloscope that show spi component does not work correctly on 8Mhz sclk.(first is on 250KHz and second picture is on 8MHz)

please regurd me how can solve this problem with spi component?

Thanks for attention...

I want to run PSoC5LP Delsig at 12 bits / 20kHz sample rate, continuous conversion mode. What is the clock frequency required at an accuracy of 0ppm, if I use an external clock to the DelSig.

hey cypress community ,

I hope you must be safe and innovating in the time of the pandemic.

I am new to power line communication and after some research is found cy8cplc10 is offering a lot of while communicating with plc. but the application note for cy8cplc10 has been obsolete (“AN52478 - Designing an external Host Application for Cypress's Powerline Communication IC CY8CPLC10) .

I wish to connect multiple slave devices on the 24v power line but i don't know why it became obsolete and if I am picking the right module for my purpose .

any suggestions will be appreciated .

Hi,

We are considering DMA for PSoC5LP.

We would like to confirm at what timing the positive edge of tqp trq becomes valid.

Could you tell us the detailed timing when the positive edge of trq becomes effective?

The data sheet of DMA componet does not include detailed timings.

Regards,