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PSoC™ 5, 3 & 1 Forum Discussions

JoBr_1593366
PSoC™ 5, 3 & 1
I'm trying to edit an existing component to replace a hardware digital input pin with a digital input terminal, so I can control it from my schematic ... Show More
abho_4730071
PSoC™ 5, 3 & 1
Hi Team,I am using serial port- DB9 connection. I am using below code. But i am getting the below output.int main(void){    uint8_t c;        CyGlobal... Show More
KaAu_4610386
PSoC™ 5, 3 & 1
Greetings,We are using CY8C5888AXI-LP096, which P4_2, P4_3, P4_4, P4_5, P4_6 GPIOs are configured as camera power enable pins. Basically, they are con... Show More
xaca_4630371
PSoC™ 5, 3 & 1
Hi everybody,I'm coding a adc lecture (14 bits) to SRAM with DMA. The idea is, save the row size of flash (255 bytes) first on the SRAM. When the tran... Show More
WaMa_286156
PSoC™ 5, 3 & 1
I want to shift *a lot* of bits out in a steady stream (without gaps between the bits).So I set up a Shift Register for a test.  I set it up to be 32... Show More
YuMa_1534086
PSoC™ 5, 3 & 1
1. USBUARTの受信バッファはUSBUART receive buffer is,(a) 何Byte有るでしょうか。   How many bytes is it?(b) そのバッファー数は、マクロか何かで知ることか出来るでしょか。    Is it possible to know the ... Show More
MiNe_85951
PSoC™ 5, 3 & 1
Hi,We are considering PSOC5LP.< Use subsystem and component >- USB FS- Timer interrupt : priority default <7>- USB interrupt : priority default <7>- U... Show More
ViTa_297566
PSoC™ 5, 3 & 1
I am reading an app note written by Cypress which is attached. Actually we are interfacing thermopile attached its datasheet also.We are able to measu... Show More
HaIn_1319421
PSoC™ 5, 3 & 1
We have developed a data logger based on PSoC5LP, external 32KHz RTC crystal, that spends most of it's time in SLEEP mode (1sec RTC interrupt enabled,... Show More
IaCa_4674211
PSoC™ 5, 3 & 1

Where do you insert the Tune word in order to change the frequency sweep?

Forum Information

PSoC™ 5, 3 & 1

The PSoC™ 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.