PSoC™ 5, 3 & 1 Forum Discussions
i want use one pin to controll ds18b20 like this
https://redacacia.me/2012/07/19/temperature-measurement-with-psoc-cy8c27643-and-ds18b20-sensor/
but cypress note said need two pins , iwant to know cy8c27443 use one pin read/write ds18b20 y/n?
Show Lesshi :
i get a sch from net cy8c27443 , The pin22 go to gnd by cap, but in my sch contact with a led and res to gnd
pin22 , i want to use pwm module this pin ,this connection is right? or not
Show LessHI,
Getting this message part way through boot loading PSoC5 with PC Bootloader Host - error message below. UART RX and TX buffers set to 64bytes as recommended and tried range of baud rates from 9600 - 115200 but still fails after a few seconds. We use the USB bootloader all the time but this is the first time we've needed to use UART/RS232. We're using a MAX3221 level shifter with the PSoC to get RS232 levels and a USB to RS232 "dongle" from the PC. Tried different USB dongles. Checked the RX and TX on a scope and they look OK.
Any other ideas?
Thanks
Show LessGreetings - I'm working on a logging project where I'm capturing data into 5x 32 bit shift registers, each with a stream of 13 words (call it a frame) with approx 100Hz clock cycle in 10 frame bursts. The design of the equipment I'm logging has reordered the 5 different data streams into 5 different bit orders even though they all represent the same data. I'd like to normalize the data back to a consistent format as I ultimately need to do a lookup of the bytes to the data values they represent. One thought I had would be a modified Shift Register with Verilog. I'll qualify this by saying I know very little about Verilog, but I'm interested in learning...
Q: Would it be possible to design a SR with the bits in a non-sequential order? My google'fu returned an example of a SR that initially started off as:
reg bit0;
reg bit1;
reg bit2;
reg bit3;
assign shift_out = bit3;
always @(posedge clock) begin
bit3 <= bit2;
bit2 <= bit1;
bit1 <= bit0;
bit0 <= shift_in;
end
And progressed to a more compact style of:
reg [3:0] bits;
assign shift_out = bits[3];
always @(posedge clock) begin
bits <= bits << 1;
bits[0] <= shift_in;
end
If the data stream was a value of 1010 and the first iteration was rearranged such as:
always @(posedge clock) begin
bit2 <= bit3; // Changed
bit3 <= bit1; // Changed
bit1 <= bit0;
bit0 <= shift_in;
end
Would that not produce 0110? Is this even possible?
The other thing I do not yet fully grasp (looking at the Cypress BSiftReg_v2_30) is how/where the values of the bits translate to the bytes from which the data is retrieved. Right now I'm going off the assumption the rearranged bit shift order would not effect the bytes output.
If what I'm trying to achieve is remotely possible, I'll bang on it till I figure it out. But if I'm barking up the wrong tree OR there's an easier way to perform bit reordering I'm open for suggestions. Just trying to take advantage of the PSoC platform and avoid software solutions. Open to suggestions,,,
TIA,
-Terry
Show LessHi,
I have a PSoC5LP device with a USBFS module in the fabric. The USB is connected to a Renesas USB 3.0 hub which is not connected to a computer.
When the PSoC starts, USBFS_Start function is called to initialize the core. However, it seems that this line inside the generated USBFS_Start function causes the hub to reset the 5V on the device causing a system reset.
(line 634 in USBFS.c)
/* Enable D+ pull-up and keep USB control on IO. */ | |
USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN; |
The interesting part is sometime it seems to work without resetting when the hub is unplugged from a computer.
When the hub is connected to a computer, it does not reset. The program executes just fine.
We had a previous generation of products based on microchip using the same hub and never experienced this problem.
Is this problem speaking to someone who experienced it in the past? Or maybe someone more experienced than me in USB can help me understand the reason behind this power reset.
Thank you.
Show LessHello,
I am trying to generate a differential test signal to send to PC by UART and I based on CE95316 but using interruptions. I designed a instrumentation amplifier with gain 1 therefore is transparent in this case (I will use it in next steps), my problem is in Vref because always is saturating in the lower limit as in the picture when Vref=Vdda/2. I also attach the project. Does anyone know why always ADC limits the lower limit and how to fix it?
Thank you in advance.
Regards.
Show LessI've been reading through the CyComponentLibrary sources installed with PsocCreator. Many of the components, like the shift register, are apparently composed of a low level component (e.g. BShiftReg_v2_30.v), and a higher-level component (e.g. ShiftRegister_v2_30.cysch.) While the higher-level component can be read in the PsocCreator schematic editor, the real guts of this component are in the Verilog file for the low-level component which is implemented (mostly) in a datapath.
Is there any way of examining a low-level component file like BShiftReg_v2_30.v at a higher level than the Verilog text, i.e. the sort of diagram produced by PsocCreator when I choose to make a new UDB document?
Show Less