PSoC™ 5, 3 & 1 Forum Discussions
Hi,
I was using the PSoC 5LP Verilog Generate when I am declaring the memory register(array of register with the command line)reg [7:0] registers[255:0] so I was creating 256 registers with width of 8, the error it's showing is:
that memory declaration is not supported. Any idea/approach what to do next.
Any another approach with how to write/read into registers, please give me the full detailed solution with your code, if possible.
Show LessIt seems everyone, mostly, agrees that DFB assembler is super hard and not to be tinkered with.
Some dedicated hobby hackers don't take no for an answer, and given that the assembler is documented in the manuals, together with a DFB asm block containing both an assembler and a simulator showing how data flows through the unit, I decided that to give it a go. The real reason for not using the filter block was that I want real time update of filter coefficients, actually just a simple PID regulator as a filter. The filter component also don't like the unstable character of PID regulators.
My findings are described at:
http://arttools.blogspot.se/2016/02/psoc-5lp-dfb-assembler.html
Comments and corrections are welcome, my time for this is limited so I cannot guarantee any fast responses, but I figure it could be helpful to collect some more help and instructions about DFB asm programming.
Regards
Magnus
Show LessThe datasheet says that the comparators may be preceded by a low pass filter. A low pass filter appears on the analogue routing diagram. The lime green is my addition. It's greyed-out.
There is no LPF in the comparator config and there isn't a LPF in the component catalogue.
How do I get my mitts on this component? It seems tantalisingly out of reach.
I bet I'm doing something silly.
PSoC Creator 4.4, Win 10, CY8C5666AXI-LP001
Show LessI just inherited code that sets a reserved bit that does make a difference in a capsense measurement. When the reserved bit is set I get "proper behavior" . I did not set this bit in a test and the capsense was reading out raw data at 255 range when it should have been reading 0. To get this design to work this bit has to be set. What does this bit do and how in the world could of my predecessor known to set it????
This bit is bit 7 in CS_CR3 that is being set by the following code segment.
CS_CR3 |= 0x90; // Reference buffer to drive the analog global bus. Bit 7 is not used so why was it set? Reserved bits should not be set. Without it the raw capsense value reads 255 instead of 0
// CS_CR3 |= 0x10; // Reference buffer to drive the analog global bus. Causes 255 to be read in raw value instead of 0 .
Then the capsense code below this.
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Hi,
i am trying to connect one SAR ADC to a two channel filter. i expect to filter each sample on both filters simultaneously.
i tried to follow ADC to Filter –Dual Channel 16-Bit Streamingusing DMA–PSoC® 3 / PSoC 5 EP58353
but i don't see any ADC nrq. first i attempted to implement ADC to SRAM and that word fine.
please help me to configure every thing.
Thanks
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Hello,
I am using a time-stamp method of measuring a frequency of a signal. The signal is a square wave, and causes a DMA transfer to start when a rising edge is detected. There is a circular RAM buffer that holds the timestamps / counts of the timer each time the input signal has a rising edge. A function is called periodically to subtract the counts from each other to estimate the frequency.
I used the example project from the CONSULTRON which is posted here:
https://community.cypress.com/t5/Code-Examples/Multi-Input-Frequency-Measurement-Tutorial/m-p/183038
Everything works as expected when I use the "Fixed Function" timer block with 16-bits. However, when I try changing it to a 24 or 32-bit UDB timer block, the counts do not make sense. The least-significant-byte of the RAM buffer always has the same value for some reason. When I look at the debug window for the component, the count matches what is expected in the MEMORY viewer, but it seems like the value at that address is not being transferred via DMA?
I referenced AN61102 which shows how to transfer 32-bit values from 16-bit spokes. I added another DMA channel as an intermediate step, and from the intermediate step goes to the larger buffer.
I was using the following #define in the DMA configuration to retrieve the counts, which is 0x4000_6508: Timer_Count_COUNTER_LSB_PTR_8BIT
Show LessHello.
Customer used CY8C5868LTI-LP039.
And they used EEPROM and DieTemp components.
When die temperature measurement is started, writing to EEPROM becomes fail.
If DieTemp_1_Start () is not called, EEPROM_1_Write () will succeed.
But EEPROM_1_Write () will fail if there is DieTemp_1_Start ().
Error status is CYRET_UNKNOWN.
Why is EEPROM_1_Write () an error?
And could you please let us know a method that EEPROM_1_Write () will succeed even if there is DieTemp_1_Start ().
Best Regards.
Yutaka Matsubara
Show LessHello,
Are there any restrictions in using DMA configuration registers (of another channel or maybe even of the same channel but another td) as destination for a DMA transfer?
I want to modify the configuration of a DMA channel (source and destination settings in td's especially) on the fly, not done by software but by (another) DMA channel, of course not during ongoing request using this data.
Devices I use are of 54xx, 56xx and 58xx series.
Thanks.
Show LessHi,
Can we just implement TPS25982 block diagram to PSoC5LP MCU. I am attaching the link for datasheet of TPS25982 and the functional block diagram
Page No:18
Please do let me know in full brief about the different blocks.
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To all,
A question was asked on an earlier form post about supporting more than 8 digits on a 7-segment LED display.
Post: LED-Driver-with-10-commons-how-it-is-possible
It is possible to support up to 24 digits with with the Cypress/Infineon LED Segment and Matrix Driver (V1.10).
Using this driver, there are only up to 8 commons supported. To use this driver for more than 8 digits you need to allocate more segments per common. This is referred to on pages 30 and 31 of the datasheet.
For example to allocate 24 digits of 7-segments (really 8-segments) you need to do the following in the configuration for 8 commons and 24 segments. If you need 16 digits you can allocate 8 commons and 16 segments. For 15 digits, 5 commons and 24 segments.
In other words, let's say you need 'x' digits. Then you need a minimum of 'y' commons. ROUNDUP(y = x/3)
segments 0-7 are used for the first set of digits (1 to x/y) and segments 8-15 for the next set ((x/y)+1 to 2x/y) and (if needed) segments 16-23 for the last set ((2x/y)+1 to x).
Each digit can be accessed in the API calls using the "position" variable.
The downside of sharing commons across digits is that it requires more current to be sourced or sunk. This can be achieved by using external components such as NPN and PNP transistors.
As a parting note: I have provided a new LED matrix driver component that can allocate up to 16 commons. This is a functional extension of the Cypress component. This component allows for separate commons drive for up to 16 digits if you need it. Additionally in a similar manner this new component can handle up to 48 7-segment digits.
The new component can be found at: Code-Examples/New-LED-Matrix-Driver-Component-Max-24-Segments-and-Max-16-Commons
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