PSoC 5, 3 & 1 MCU

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KeTa_1875721
PSoC 5, 3 & 1 MCU
I am using an CY8C21534-24PVXI part using a UART block version 5.3 Have it set up to use both tx and rx interrupts, modified boot.tpl accordingly. Am ... Show More
immanuel
PSoC 5, 3 & 1 MCU
How can I read the unique id from PSoC 5LP devices within ppcli?Refering to PSoC 5LP Registers TRM and according to code generated (CyLib.c and cydevi... Show More
linardsee
PSoC 5, 3 & 1 MCU
Hello, I need to implement USB mass storage device (using MSC class) on PSOC CY8C5267LTI-LP089 chip. For storage I am going to use SPI flash. Thanks t... Show More
RoRo_4659551
PSoC 5, 3 & 1 MCU
Hi, I am trying to configure multiple pins connected to interrupts but I receive an error [see attached pictures].       Thanks, Roy Roif   @Motoo_Tanaka... Show More
DaBa_1448511
PSoC 5, 3 & 1 MCU
I had placed all my components in my project based on CY8CKIT-059, including a Capsense linear slider, using five PSoC pins diplexed, resulting in ten... Show More
Dudi_Ildis
PSoC 5, 3 & 1 MCU
We are using the UART with the HW fifo of 4, we find that when disabling interrupts for long time (not for 4 fifo long), we start to loss bytes someti... Show More
user_4495571
PSoC 5, 3 & 1 MCU
Hi, after updating the Programmer App it asked for updating the MiniProg 4 firmware. I made the mistake to agree. Now, I'm no longer able to connect t... Show More
IlanMazuz
PSoC 5, 3 & 1 MCU
Hi, I need to convert the code example that you can find in PSOC 4 kit 037 to PSOC 5LP PN:CY8C5888LTI-LP097. The code example his name is sensor BLDC ... Show More
PaFi_4802396
PSoC 5, 3 & 1 MCU
I am trying to create a master SPI using PSOC 5. For debugging purposes I've set the clock to be 5 Hz (so I can track the sent and received data in re... Show More
GrCa_1363456
PSoC 5, 3 & 1 MCU
Using a PSoC 5 kit, CY8CKIT-059, the I2C running at 100kHz occasionally locks up at extreme cold ~ -25 to -40. Are there know issues with the PSoC 5 a... Show More
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PSoC 5, 3 & 1 MCU

The PSoC® 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.
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