Using 60MHz as Master clock and bus clock for my project, I ran into some setup time issues between various components in my design, so I decided to use a slower 30MHz clock (which I dubbed CLK_DIV2) for my components except where a faster clock is needed. I figured that that would give the fitter some more room to find a solution, and it seems to have improved things somewhat.
I am using another clock (CaptureClock, 6MHz, derived from CLK_DIV2 with a divider of 5) to capture data into a FIFO, using the FIFOIn component from the PSoC Sensei blog. The captured data is synchronized to CLK_DIV2.
I would expect the path delay requirement for the captured data from the sync blocks to the FIFO to be at 30MHz, since the source clock has that frequency and the destination clock is divided down from the source clock (and thus should be "in phase" with it). However, when investigating more timing warnings I found that the report file shows a 60MHz requirement.
Looking into the TRM I saw that the CaptureClock will not really be divided down from CLK_DIV2 but instead both will be derived from the BUS_CLK, but I see no reason why they couldn't be set up to be "in phase" so that there will always be two BUS_CLK cycles between a rising edge on CLK_DIV2 and a rising edge on CaptureClock.
I can achieve what I want using the Frequency Divider component, but that takes up UDB resources and may put more "pressure" on the fitter again.
So: Is there a way to configure my two clocks CLK_DIV2 and CaptureClock so that the path delay requirement between them is determined by CLK_DIV2 instead of by the master clock?
