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Can someone explain why the VDAC output is not zero volts when it is set to zero?
My test showed a voltage of 1.4mV when I set the VDAC to zero. Is this simply a voltage offset orginating from a buffer used in the component? I'm not sure of the exact design of the VDAC, but I do know that it is based on the IDAC.
VDAC offset can be a maximum of 1LSb. This is 4mV in 1V mode and 16mV in 4V mode. In additon, if you are using an Op-Amp to buffer VDAC output, the Op-amp offset(max 1.5mV) will be an addition contribution