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I have established that there are 24 UDBs in the PSOC5. those UDBs can be configured using verilog. my question is: how much is the size of these UDBs (in logic gates term like in xilinx or Altera FPGAs)?? does every UDB have to be configured independently or can I just use them all at once?? so suppose I have a code that is bigger than 1 UDB, can I use 2 or more to implement it?
More than PLDs & macro-cells, each UDB has a 8-bit Datapath which is like a mini-CPU. You can program them using Verilog code and use it for state machine based designs so that you can save PLDs for other glue logics.