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PSoC 5, 3 & 1 MCU

Anonymous
Not applicable

I have established that there are 24 UDBs in the PSOC5. those UDBs can be configured using verilog. my question is: how much is the size of these UDBs (in logic gates term like in xilinx or Altera FPGAs)?? does every UDB have to be configured independently or can I just use them all at once?? so suppose I have a code that is bigger than 1 UDB, can I use 2 or more to implement it?  

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5 Replies
Bob_Marlowe
Expert II

Have a look here http://www.cypress.com/?rID=69959 at what USBs and Datapath are.

   

 

   

Happy reading

   

Bob

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Bob_Marlowe
Expert II

Some more...

   

http://www.cypress.com/?rID=40410

   

http://www.cypress.com/?id=2401

   

 

   

Bob

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HeLi_263931
Honored Contributor II

tl;dr:

   
        
  • each UDB contains 8 macro cells (like in a PLD), which gives 192 macro cells
  •     
  • but additionally, each UDB contains a programmable ALU and a FIFO (called the DataPath), which changes it into a small CPU core
  •    
   

In my understanding, when using only the PLD capabilities (the macro cells), one programs the whole PSoC. But when using the DataPath, the chaining needs to be explicit (though it is simple).

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HeLi_263931
Honored Contributor II

The forum software screwed it up again 😞 The posting above should have a buletted list instead of simple lines...

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Anonymous
Not applicable

 More than PLDs & macro-cells, each UDB has a 8-bit Datapath which is like a mini-CPU. You can program them using Verilog code and use it for state machine based designs so that you can save PLDs for other glue logics.

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