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I have established that there are 24 UDBs in the PSOC5. those UDBs can be configured using verilog. my question is: how much is the size of these UDBs (in logic gates term like in xilinx or Altera FPGAs)?? does every UDB have to be configured independently or can I just use them all at once?? so suppose I have a code that is bigger than 1 UDB, can I use 2 or more to implement it?
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PSoC 5LP
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tl;dr:
- each UDB contains 8 macro cells (like in a PLD), which gives 192 macro cells
- but additionally, each UDB contains a programmable ALU and a FIFO (called the DataPath), which changes it into a small CPU core
In my understanding, when using only the PLD capabilities (the macro cells), one programs the whole PSoC. But when using the DataPath, the chaining needs to be explicit (though it is simple).
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The forum software screwed it up again 😞 The posting above should have a buletted list instead of simple lines...
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More than PLDs & macro-cells, each UDB has a 8-bit Datapath which is like a mini-CPU. You can program them using Verilog code and use it for state machine based designs so that you can save PLDs for other glue logics.