Hi guys,
I have build a new component with the UDB Editor. Now I try to parameterize the data path width.
With varilog this can be done through defining a hardware parameter and separate the code with a if else construct.
But for simplicity I'd like to use the UDB Editor and with this graphical tool I do not find a solution for the problem.
Please Help!
Welcome in the forum, Michael.
This will not work using UDB editor, must be done in verilog,
Bob
Hi,
thanks for the ultra fast answer! I feared that I will get such news 😞
Anyway than I have to edit the varlog file at the end.