Strictly necessary cookies are on by default and cannot be turned off. Functional, Performance and Tracking/targeting/sharing cookies can be turned on below based on your preferences (this banner will remain available for you to accept cookies). You may change your cookie settings by deleting cookies from your browser. Then this banner will appear again. You can learn more details about cookies HERE.
Strictly necessary (always on)
Functional, Performance and Tracking/targeting/sharing (default off)
I'm trying to use a UDB clock enable to create a gated clock for a bunch of shift registers and a counter.
The input clock (to the clock enable) is just a 1MHz clock generated by the PSoC. The enable signal is a control register bit. The output of the UDB clock enable *only* connects to the clock input of 6 ShiftReg_v2_30 blocks and a Counter_v2_40 block which has been configured to use UDB (not fixed function).
When I go to build the application, PSoC Creator explodes, saying "The UDB Clock/Enable components may only drive clocks in UDB content and \MyUDBEn:udbclkenable\ is connected to clk_en on \MyShiftReg:bSR:ClkEn\" -- the same error is repeated for what I am guessing is every register the clock enable output touches in each of the modules.
I do notice that some PSoC component blocks have a pink header and most have a green header, and I am guessing that that has something to do with why I can't get this to work.
On a more general note, what is the correct way to generate a glitch-free gated clock for PSoC components?