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PSoC 5, 3 & 1 MCU

New Contributor II

Hey there,

   

I am currently playing around with the PSoC5 to create a true random number TRNG generator (not pseudo random, PRS).

   

I found some snippets on stackoverflow:
http://stackoverflow.com/questions/14497877/how-to-implement-a-pseudo-hardware-random-number-generat...

   

But I failed to implement them, as PSoC creator keeps on optimizing the circular structures and the "keep" attribute seems not to help.

   

So... how can I force PSoC Creator to prevent optimization or you have some idea on how to generate true random numbers on the PSoC5 (no external pins shall be used to capture noise or similar).

   

 

   

Regards

   

Thomas

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Employee

You can go to Compiler settings in Build option,there is an option for setting optimizations as None.

   

For more information on optimizations available,go through this document by GCC on optimize option available-

   

https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html

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Honored Contributor II

In Project->build options-> code generation, there is a section "optimization". Try to play with settings. Though in my experience it has no effect on Verilog.

Employee

You can go to Compiler settings in Build option,there is an option for setting optimizations as None.

   

For more information on optimizations available,go through this document by GCC on optimize option available-

   

https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html

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New Contributor II

Im afraid the GCC optimization level has no impact on the HDL Synthesis or am I wrong?

   

Ill give it a try later

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New Contributor II

Ok.

   

In "Code-generation" I can control the synthesis options. I turned off all the optimization levels but I need to give syn_keep as custom parameter. I can not find help for that, how is the syntax?

   

Error:

   

Warning-1361: The design contains a combinational loop. Check the design for unintentional latches. Breaking the loop at \TRNG_1:stage_1\/q --> \TRNG_1:stage_1\/main_0

   

I could imagine that cypress wants to prevent loops that could destroy the chip but trust me, I absolutely know what I am doing ;-)​

   

 

   

I tried to post the code but I get an error...

   

I use the Galois Ring Oscillators(GARO) from http://stackoverflow.com/questions/14497877/how-to-implement-a-pseudo-hardware-random-number-generat...

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Honored Contributor II

Borstenhorst,

   

there is an older thread re: optimization off:

   

http://www.cypress.com/comment/229921#comment-229921

   

 

   

Try to post your project: click project name in workspace explorer -> File -> Create workspace bundle -> minimal. If you get an Error during upload, open Cypress support case. I just contacted Cypress on similar issue (image uploading didn't work) and they resolved the issue. It appears that Cypress is re-designing the website and that creates a havoc.

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Honored Contributor II

> ...need to give syn_keep as custom parameter.

   

For example of passing a parameter to Verilog file, check this custom component demo, where a "bus width" is being passed to Verilog file as a parameter.

   

http://www.cypress.com/comment/352766#comment-352766

Anonymous
Not applicable

Some months ago remake this

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New Contributor II

Hi all,

   

 

   

JLS1, your component is basically the same like the code I implemented. It seems like I made a mistake somewhere in the schematic, as your module gives me (at least I thinks so) random values.

   

The next step is to put the values in dieharder or similar, in order to find out if they are truly random.

   

I will test that in the next weeks.

   

Thanks a lot guys!