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This is more a thought design than something I'm actively working on, but:
I want to parse a bitstream. The bitstream contains pulses which are either aligned on a clock pulse or between two clock pulses. There is no explicit clock signal, but I know the rough clock speed and there are sync sequences embedded in the bitstream.
(It's actually the incoming bitstream from a floppy disk drive. It's MFM encoded, with an underlying clock of about 500kHz. But the details aren't important.)
It seems that the most sensible way to parse the bitstream is to trigger on the incoming bitstream pulse, and then sample on a 1MHz clock. That way I can tell from whether the clock signal is high or low about what kind of pulse it is. That seems relatively straightforward (although I'm sure the devil's in the details).
However... my bitstream isn't going to be exactly 500kHz, because it's going to be generated by ancient and unreliable mechanical hardware, i.e. floppy disk drives. So I need to somehow sync my clock against the incoming pulses. Given that PLLs are designed around synchronising against external clocks, I would naively expect to just generate the appropriate rate of clock and connect it up to my input bitstream, and it would automatically resync based on every pulse.
Is that realistic on a PSOC5?
Looking at the Clock component, I don't see any way to provide an input sync source. There are some mentions of synchronisation but nothing that looks useful. There's a Sync component, but I don't think it does what I want. Can I build a PLL out of analogue components? Can I configure the SCB to do this for me out-of-the-box? Where, basically, should I start looking?
It seems reasonable that this is possible; after all, it's basically a UART...
...or (and this isn't my idea, someone else suggested it):
Create a high-speed timer at, say, 8MHz. Whenever I receive a incoming bitstream pulse, sample the timer and then reset it. The intervals will nicely bucket into 1, 1.5 or 2 ticks depending on the MFM transition type; figuring out which is a couple of comparisons. That will then feed my MFM decode state machine directly.
This avoids the need to maintain and synchronise the bitstream clock entirely. It'll naturally resynchronise based on the incoming bitstream and the margins are completely under my control based on where I put the bucket boundaries. It plays better to the Psoc5's strengths, too.
I did look at the UART component, but AFAICT you have to have one start bit and at least one stop bit. I don't think (haven't found an actual confirmation yet, though) that my bitstream has these: it's just eight-bit byte groups one after another. And with the MFM encoding I think I would actually be needing to record 15-bit groups before doing the decoding...