cancel
Showing results for 
Search instead for 
Did you mean: 

PSoC 5, 3 & 1 MCU

JoCa_263971
New Contributor

Hello everyone, I am looking for your help in solving the following case:

I need to sample in parallel two sine signals.

For this, I have two ADCs (SAR) in PSoC5LP working at 1 Msps, as shown in the figure below. Each of the bypass capacitors have been connected to the PSoC5 pins and the configure system clock meets the requirements for the mentioned sampling frequency.

Schematic.jpg

Clock System Configuration.jpg

Each "eoc" output of these ADCs is connected to a separate DMA channel which stores the respective ADC data (ch1 and ch2).

Activation of the DMA channels and the start of conversion of the ADCs are carried out with the firmware using the following APIs:

     CyDmaChEnable(DMA_Ch1_Chan, 1);

     CyDmaChEnable(DMA_Ch2_Chan, 1);

     ADC_Ch1_StartConvert();

     ADC_Ch2_StartConvert();

Then, if I use the same input sine signal for the two ADCs (Pin_Ch1 and Pin_Ch2) and assuming that the acquisition happens in parallel, the graphs of the results should overlap.

However, it is obvious that there is a delay, but I have not managed to be "constant" and therefore the results are random. That is, sometimes the results overlap and in other cases the data have delays.

So how can I achieve my parallel acquisition requirement or with a constant delay?

What are your tips?

regards

JJ

0 Likes
Reply
1 Solution
HeLi_263931
Honored Contributor II

Instead of the common SOC signal, just start the clock only after the ADCs got started. (I did this in a past project, works fine)

View solution in original post

5 Replies
HeLi_263931
Honored Contributor II

You can use the start conversion external signal of the ADCs. Route it to a control register and use this to start conversion.

0 Likes
Reply
JoCa_263971
New Contributor

Thank you user_78878863 for the answer and suggestion. In this way, the two ADCs start at the same time. But the start of conversion signal only allows one sample.

So, to my case, what is your additional advice if I need a burst of samples (eg, 500)? 

0 Likes
Reply
HeLi_263931
Honored Contributor II

Instead of the common SOC signal, just start the clock only after the ADCs got started. (I did this in a past project, works fine)

View solution in original post

odissey1
Honored Contributor II

Define amount of DMA data transferred in DMA channel settings. In DMA_done isr, stop ADC and reset soc signal to zero. Once accumulated data is processed, repeat soc.

JoCa_263971
New Contributor

user_78878863, It was a good strategy to control start/stop of the clock signal after starting the ADCs. Some minor adjustments and now everything works well. Thank you very much for your help.

JJ

0 Likes
Reply