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PSoC 5, 3 & 1 MCU

MaWa_283831
New Contributor II
        Shift Register v2.30 component seems to have some issues.   
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JoMe_264151
Expert II

Yes, an unsynced clock will not work for sure.

   

The shift-register is made using a datapath object which is clocked by the master-clock. Async clocks for shifting will probably fail. I think there should be a hint in the shiftreg datasheet or a warning.

   

 

   

Bob

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MaWa_283831
New Contributor II
        I load the first register with 0x07 and after a while, the bits in both registers are 1. If I load the first register with 0x03, after a while both registers are 0. Second register is always set to 0 initially. This is with my new CY8CKIT-059 and all dev software updated to lastest version.   
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JoMe_264151
Expert II

Matt,

   

Can you post your complete project or at least a reduced version that shows the error, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.



Bob
 

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MaWa_283831
New Contributor II
        Okay, I stripped the project down to the bare minimum and the issue does still exist. I'm hoping it is something simple I overlooked. I do have another brand new 059 kit I can test on, but I'd like to leave it pristine if possible. The project has a console connection so you can see the results via software as well as observe the LED.   
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MaWa_283831
New Contributor II
        Well Bob, having seen this anomaly before, I tried purifying the clock and now it works fine. So I'm curious as to why a warning wasn't issued during compilation.   
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MaWa_283831
New Contributor II
        This may be the best workaround method.   
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JoMe_264151
Expert II

I did not read your last post yet, will check later.

   

Correwcted the clock within your system to 2 Hz synced to sysclock, now the led shows corrwect signal.

   

Check in clock view the frequency, I needed a prescaler.

   

 

   

Bob

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JoMe_264151
Expert II

Yes, an unsynced clock will not work for sure.

   

The shift-register is made using a datapath object which is clocked by the master-clock. Async clocks for shifting will probably fail. I think there should be a hint in the shiftreg datasheet or a warning.

   

 

   

Bob

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