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Hi
I am trying to implement a SIPO shift register using a LUT. Has anyone done this before? I have looked at the document by Xilinx
www.xilinx.com/support/documentation/application_notes/xapp465.pdf
I do not want to use the Shift register provided in PSoC Creator because the output is only accessible using DMA or CPU but i want to access it in hardware because i need to act on the actually bits to be shifted out.
Regards
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It would be better to use verilog-programming. Attached is a simple example.
Create a new component and use it. there are some videos on constructing components using verilog, have a look at this thread http://www.cypress.com/?app=forum&id=2492&rID=41954
Bob
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It would be better to use verilog-programming. Attached is a simple example.
Create a new component and use it. there are some videos on constructing components using verilog, have a look at this thread http://www.cypress.com/?app=forum&id=2492&rID=41954
Bob
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I would concur,
verilog is likely the way to go. Its pretty much like C anyhow. Or maybe I'm just on a hardware kick.
programming the datapath is a little more involved than just the verilog; I think mostly because it involves thinking about programing in parallel (and a couple extra registers and instructions), but a shift register in the datapath is pretty straight forward. Somehow after a bit of trial and error, I did manage to get a 32 bit input shift register using one 8 bit datapath that loaded the 4 bytes into one of the FIFO.
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could you share how you achieved the 32bit SR in datapath?
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My code is a disaster (there are more debug wires and registers than actual wires and registers needed), but essentially I had:
input serial clock wire
input serial data wire
enable
Datapath was set up to shift left (or right as you wish) with a serial input, and clocked on the serial clock.
I set up a down counter in verilog to count 8 clocks -- first I did a verilog down counter, then I used an instance of the count_7 (both worked, just use resources differently). The output of this counter would go high for one clock of the input serial clock, and this would trigger a capture to the F0 (clocked in fast mode, edge sensitive). Fifo can hold up to 4 values, then CPU or DMA can deal with a union.
You can do all this without verilog and wiring up the standard components too, though I did have trouble figuring out how to get that last shifted value captured (needed just one more clock edge).
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Hi Maduna,
I see your post below on the SIPO shift register. I faced the same issue that the standard PSoC Creator component only allowed access of the output through CPU or DMA. As you said i want to access the received serial bits and act on the bits to be shifted out.
Did you have a solution already as a component. Can you please post it.
Best Regards
Robin
Hi
I am trying to implement a SIPO shift register using a LUT. Has anyone done this before? I have looked at the document by Xilinx
www.xilinx.com/support/documentation/application_notes/xapp465.pdf
I do not want to use the Shift register provided in PSoC Creator because the output is only accessible using DMA or CPU but i want to access it in hardware because i need to act on the actually bits to be shifted out.
Regards
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Seems to me you can use verilog.
See attached project, but a big warning it is UNTESTED.
module shifter (
output [7:0] parallel_out,
input clock,
input enable,
input reset,
input shift_in
);
//`#start body` -- edit after this line, do not edit this line
reg [7:0] tmp;
always @(posedge clock or posedge reset)
begin
if (reset) tmp <= 7'b0;
else tmp <= {tmp[6:0], shift_in};
end
assign parallel_out = tmp;
//`#end` -- edit above this line, do not edit this line
endmodule