- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi, While trying to test hibernation of Psoc5LP (cy8c5868axi-032LP) to minimize power consumption I have lost the device. This means J-LINK is unable to detect the device over SWD. I configured the SWD pins as GPIO as suggested by power management in order to obtain lowest possible power consumption. The SWD port shoult be possible waken up after reset and the GPIO pins will be SWD again. But I fail to access the SWD port with J-LINK programmer.
I wonder if there is some trick that the programmer must do and the J-LINK does not do that. Any experience?
I attached the project that will brick the device for me in order you can see maybe there is something else wrong too. I have carefully verified the bricking flag of firmware protection.
Solved! Go to Solution.
- Labels:
-
PSoC 5LP
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The SWD settings has nothing to do with programming the chip. There is a sequence shortly after reset or power-up where a programmer can gain control. The setting of the SWD/GPIO pins is done during the programming cycle. When your chip is not seen by your system try a complete reset (PC, programming hardware etc). Specs for the programming are shown in the resp. app notes.
Bob