SR Flip Flop initial state

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NiNa_4043086
Level 3
Level 3
First like received

Hello,

I am designing a firmware using PSOC creator for PSOC5LP and I would like to use SR-FF components in my design.

In my design some of SR-FF will have '0' logic on both S and R input pins after power on.

In that case what would be the output?

Many thanks.

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Ekta_N
Moderator
Moderator
Moderator
750 replies posted First like given 250 solutions authored

Hello,

My sincere apologies for the confusion caused. We discussed with component experts and found that SR FF is implemented using D FF. Since the D FF is initialized to zero at power up and device reset, the initial state of SR FF after reset and power up will also be zero.

You can also have a look at the PSoC 3, PSoC 4, and PSoC 5LP Digital Design Best Practices Appnote:   https://www.cypress.com/file/179061/download

Best Regards

Ekta

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