Jul 09, 2019
11:01 PM
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Jul 09, 2019
11:01 PM
Hello,
I am designing a firmware using PSOC creator for PSOC5LP and I would like to use SR-FF components in my design.
In my design some of SR-FF will have '0' logic on both S and R input pins after power on.
In that case what would be the output?
Many thanks.
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PSoC 5LP
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Jul 19, 2019
04:37 AM
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Jul 19, 2019
04:37 AM
Hello,
My sincere apologies for the confusion caused. We discussed with component experts and found that SR FF is implemented using D FF. Since the D FF is initialized to zero at power up and device reset, the initial state of SR FF after reset and power up will also be zero.
You can also have a look at the PSoC 3, PSoC 4, and PSoC 5LP Digital Design Best Practices Appnote: https://www.cypress.com/file/179061/download
Best Regards
Ekta
8 Replies