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I'm trying to communicate with an external ADC. Therefore I use SPI with manual SS control. To emulate the ADC a took a SPI slave next the SPI Master on the top design. When setting the clock speed to 1kHz, I see the expected result on the LCD, but when increasing the speed to 1MHz or higher I get corrupted data.
I attached my workspace bundle and a picture of my setup wth the expected result on LCD. It would be nice if someone could take a look at my code and eventually find my mistake.
Sorry for the late reply, may be you already fixed the problem but any way i write here what i found about your project.
1. The reset signal (in both components) is not connected to anything, this must be connected to a logic 0.
2. The MOSI_M signal is routed to the P3_2 pin, this pin has a CAP connected to it, you should route this signal to anywhere else. The following image is from the CY8CKIT-059 kit schematic available in the instalation location, in my case here C:\Program Files (x86)\Cypress\CY8CKIT-059\1.0\Hardware
3. This is personal preference, but i configured the CS_M to have a pull-up.
4. You forgot to put the CS_M low in the while (flag<2) loop, right at the beginning, before the SPI_M write.
5. I have not a LCD but i used a UART to see the results, find the project attached.