Showing results for 
Search instead for 
Did you mean: 

PSoC 5, 3 & 1 MCU

New Contributor II

We are putting together a simple SPI based controller to talk to LPD8806 LED driver ICs for addressing multiple LEDs in a large array using a PSoC 5 (overkill at the moment but that's what we have lying around!).


The driver ICs use a simple, one directional (no feedback) serial data protocol with Clock and data lines (data sheet attached) so we are using an SPI-Master component to drive it.  Looking at the "Mode" settings the driver ICs need to read the data on the rising edge of the clock 90 degrees out of phase with the data - this equates to the CPHA = 0, CPOL = 0 settings for the SPI_Master.  However, looking at the scope on the data and clock lines they are in phase with these settings.  In fact I have tried all four possible combinations of CPHA/CPOL and they are always in phase - scope screen shot attached.


I am obviously doing something wrong but can't work out what it is.  Any ideas?


By the way, these are great LED driver ICs, very cheap and flexible. 


Many thanks


PS - The application is actually functioning as it is but I'm concerned that it is probably running "on the edge" and want to get it right to ensure it is robust.  In case you're interested, the attached photo shows the proof-of-principal panel of 144 leds - production units will have over 2500 addressable LEDs.

1 Reply

The maximum component clock frequency is derived from tSCLK_MISO in combination with the routing path delays of the SCLK input and the MISO output . These “Nominal” numbers provide a maximum safe operating frequency of the component under nominal routing conditions. It is possible to run the component at higher clock frequencies, at which point you will need to validate the timing requirements with STA results.


So ,at what clock frequency you are running the Component SPIM.


Please zoom more the Clock and data scope image.


Please attach your project if possible