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When I gate the SPI clock with a control register and inverter, the DAC works when a small delay (~20us) is introduced at the end of my write routine. This is with clock phase = 0 and polarity = 0. Even without gating, the delay is still necessary when operating in clock phase = 0 and polarity = 1 mode when driving the DAC only.
When the clock phase = 1 and clock phase = 0, this delay is not necessary.
I think since the DAC is not ordinary SPI, the delay holds the SYNC line low long enough to allow data to be latched. The phase difference has the same effect as well.
The delay is not an issue in this application since speed is not critical. Would I be best off writing my own driver if speed were critical? Or can PSOC's SPI master somehow drive the DAC properly without tinkering with delays and the phase?