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PSoC 5, 3 & 1 MCU

New Contributor II

I have an application where I am driving a TI DAC8564IAPW DAC and an MCP23008 GPIO expander on the same bus.

   

The problem I am having is that the clock polarity and phase needs to be set to CPHA = 1 and CPOL = 0 to drive the DAC. I have the CS line always asserted and the SYNC line on the SPI chip select.

   

The MCP23008 simply uses ordinary SPI (CPHA = 0 and CPOL = 0).

   

There is no way in software to change between the two modes. I have alternative ideas but would be time consuming to implement. What would the easiest method be to address this issue?

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Esteemed Contributor II

Not being a guru on SPI, but won't it be sufficent to invert the clock at need using an XOR and a control register?

   

 

   

Bob

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New Contributor II

When I gate the SPI clock with a control register and inverter, the DAC works when a small delay (~20us) is introduced at the end of my write routine. This is with clock phase = 0 and polarity = 0. Even without gating, the delay is still necessary when operating in clock phase = 0 and polarity = 1 mode when driving the DAC only.

   

When the clock phase = 1 and clock phase = 0, this delay is not necessary.

   

I think since the DAC is not ordinary SPI, the delay holds the SYNC line low long enough to allow data to be latched. The phase difference has the same effect as well.

   

The delay is not an issue in this application since speed is not critical. Would I be best off writing my own driver if speed were critical? Or can PSOC's SPI master somehow drive the DAC properly without tinkering with delays and the phase?

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Esteemed Contributor II

In a PSoC5 you could use two SPIM components and mux clock and data.

   

 

   

Bob

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New Contributor II

If it was SCB then you can keep the device in unconfigured mode and configure it using firmware. I dont think it is possible to do the same using PSoC5LP.

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