PSoC 5, 3 & 1 MCU

[Anonymous]

I have an option to run the code from SRAM in PSoC 5. Is there a similar option in PSoC 3 to run the code from SRAM. How do I do it?

[Anonymous]

To my understand. PSoC3 cannot excute code in RAM.

[Anonymous]

 Just wondering if PSoC4 can have code excute in RAM?

[ETRO_SSN583]

Answer is yes, PSOC 4 and 5 address space is linear, modified von neumann, as opposed to

   

PSOC 3, Harvard.

       

Regards, Dana.

[JoMe_264151]

Did John von Neumann study at Harvard? (smiley)

       

Bob

[Anonymous]

 In ARM Cortex-M3 architecture, lower 0.5GB (0x00000000 – 0x1FFFFFFF) represents code memory.

   

In PSoC 5LP, lower 32KB SRAM is present in 0x1FFF8000 – 0x1FFFFFFF memory location which is in code memory space of CM3. That is why it is possible to execute the code from SRAM provided that code is stored in this lower 32KB of SRAM space.

[Anonymous]

In PSoC 4, 4KB of SRAM starts from 0x20000000 location only which is not in Code space region. So, it is not possible to execute code from SRAM of PSoC 4 which is possible in PSoC 5LP.

[ETRO_SSN583]

In the TRM it shows that code can be executed out of SRAM, see attached

       

Regards, Dana.

[ETRO_SSN583]

This seems to support it as well -

       

http://www.google.com/url?sa=t&rct=j&q=cortex%2BM0%2Bcode%2Bexecution%2Bsram&source=web&cd=3&ved=0CD...

           

Regards, Dana.

[Anonymous]

 I think we should move this thread to PSoC4 sub forum.

[ETRO_SSN583]

        The thread is essentially complete, no need to move it. Regards, Dana.   

[Anonymous]

Hi,

       

In PSoC 5LP, it is possible to place a code in the upper SRAM region (i.e) above the address 0x2000000. Similarly in PSoC 4, it is possible to possible to place a code in the upper SRAM region. There is no limitation that the code in the upper SRAM region cannot be exectued.

       

Regards,

   

Asha