In ARM Cortex-M3 architecture, lower 0.5GB (0x00000000 – 0x1FFFFFFF) represents code memory.
In PSoC 5LP, lower 32KB SRAM is present in 0x1FFF8000 – 0x1FFFFFFF memory location which is in code memory space of CM3. That is why it is possible to execute the code from SRAM provided that code is stored in this lower 32KB of SRAM space.
In PSoC 4, 4KB of SRAM starts from 0x20000000 location only which is not in Code space region. So, it is not possible to execute code from SRAM of PSoC 4 which is possible in PSoC 5LP.
In PSoC 5LP, it is possible to place a code in the upper SRAM region (i.e) above the address 0x2000000. Similarly in PSoC 4, it is possible to possible to place a code in the upper SRAM region. There is no limitation that the code in the upper SRAM region cannot be exectued.