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Hi,
to reduce the resource requirements of my design I consider the use of DP. I wrote the FSM in pure verilog without DP components and the PSoC is up to 98% full.
Anyway, the idea is to load a timer by using a verilog hardware period register (which is written by another verilog instance). The common approch of the DP Video Tutorials AN 21{1-4} is to use CPU registers to load the period into e.g. D1 or even F1. Now I need to load it from PI port of cy_psoc3_dp (which offers the possibility to do this). But I can't use it for comparision usage since the condition signals generator by the DP is limited to the internal registers A{0,1} or D{0,1}. Further more it seems that I can't load the external register value to a fifo register Fx and than load it to an Dx register since there is no parallel port in.
To be short: How can I configure the DP for an external period register - e.g. the 16-bit PWM example with verilog limit and period register?
Thanks
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PSoC 5LP