Psoc 5LP Hardware triggers Timer -> Timer triggers PWM?

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
ChGa_3545231
Level 2
Level 2
First like given

Hi there,

in my current project I have the following problem:

A dig. signal triggers a PWM every 20ms. The PWM runs for 10ms and stops for the next 10ms.

I want the PWM to run for 20ms (2 cycles). Therefor I thought I could not only trigger a PWM via the dig. Signal but also the Timer component.

The Problem is the Timer should be triggered to the exact same time as the PWM. Then it should count 10ms and after that it should trigger the PWM.

I already tried all different settings for the Timer component but nothing seemed to work.


Does somebody have some ideas on how to implement this the correctly?

Kind Regards

Christoph 

0 Likes
1 Solution
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Dear Christoph-san,

Yesterday, when I read problem for the first time, I thought what you wanted were

(1) I thought you were thinking of running 2 cycles (10ms per cycle)

000-type1.JPG

But when I re-read, it seems to be more likely

(2) PWM 1cycle = 10ms (There is only one flipping of level in 10ms)

In this case, setting PWM with "Run Mode: One shot with Multi Trigger"

and trigger the PWM every 20ms would take care of it.

001-type2.JPG

But in general following seems to make better sense to me

(3) Some higher frequency (=cycle) PWM runs for 10ms and stops for 10ms

002-type3.JPG

Which one is the timing you are thinking?

Or you are thinking of some other pattern?

> I think your solution is pretty close to fixing that issue

> but how do get sure that the period is set the exactly 10ms?

> By changing the clock you will never be able to getting a fixed timing, if I am right.

You are right if we modify the clock (this time the clock to dff, right?),

there should be some gate delay.

Now, how "Exact" do you need the timing?

In the 58LP datasheet there is a Table 6-1. Oscillator Summary

003-clock-table.JPG

Unless you connect an external crystal or clock, IMO is +/- 1% @3MHz, +/- 7% @74MHz.

And I think (hope) that the delay of a gate in PSoC 5LP should be in the order of ns.

Anyway, let me think about (3), unless it's not what you want.

Best Regards,

18-Feb-2020

Motoo Tanaka

View solution in original post

7 Replies
lock attach
Attachments are accessible only for community members.
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

If you trigger pwm every 20ms and during the 20ms the pwm runs 2 x 10ms cycles

sounds that you can just use a continuous mode of a 10ms cycle pwm to me.

So I interpreted that you want run 2 cycles of pwm with every trigger.

When I push SW2, pwm runs 2 cycles then stops. (LED blinks twice)

I tried with CY8CKIT-059

schematic

000-schematic.JPG

main.c

==========

#include "project.h"

int main(void)

{

    CyGlobalIntEnable; /* Enable global interrupts. */

   

    PWM_Init() ;

    for(;;)

    {

        /* Place your application code here. */

    }

}

==========

moto

Hi Moto,

Thank you very much for your response.

You are right I am getting a signal every 20ms, but I need to trigger the PWM every 10ms. In order to keep it from running away and therefor having timing issues, I want the PWM to be triggered by hardware every 20ms. Then a Timer or whatever block that can give me a signal after 10ms to trigger the PWM again.

I think your solution is pretty close to fixing that issue but how do get sure that the period is set the exactly 10ms? By changing the clock you will never be able to getting a fixed timing, if I am right.

Kind Regards

Christoph 

0 Likes
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Dear Christoph-san,

Yesterday, when I read problem for the first time, I thought what you wanted were

(1) I thought you were thinking of running 2 cycles (10ms per cycle)

000-type1.JPG

But when I re-read, it seems to be more likely

(2) PWM 1cycle = 10ms (There is only one flipping of level in 10ms)

In this case, setting PWM with "Run Mode: One shot with Multi Trigger"

and trigger the PWM every 20ms would take care of it.

001-type2.JPG

But in general following seems to make better sense to me

(3) Some higher frequency (=cycle) PWM runs for 10ms and stops for 10ms

002-type3.JPG

Which one is the timing you are thinking?

Or you are thinking of some other pattern?

> I think your solution is pretty close to fixing that issue

> but how do get sure that the period is set the exactly 10ms?

> By changing the clock you will never be able to getting a fixed timing, if I am right.

You are right if we modify the clock (this time the clock to dff, right?),

there should be some gate delay.

Now, how "Exact" do you need the timing?

In the 58LP datasheet there is a Table 6-1. Oscillator Summary

003-clock-table.JPG

Unless you connect an external crystal or clock, IMO is +/- 1% @3MHz, +/- 7% @74MHz.

And I think (hope) that the delay of a gate in PSoC 5LP should be in the order of ns.

Anyway, let me think about (3), unless it's not what you want.

Best Regards,

18-Feb-2020

Motoo Tanaka

lock attach
Attachments are accessible only for community members.
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Dear Christoph-san,

I tried the case (3) with CY8CKIT-059

schematic

Note:

Clock_1 should be 10kHz, although I set it to 1kHz so that I can see the LED.

Clock_2 should be the frequency you need for the PWM.

Timer needed to be "Run Mode: Continuous" to receive multiple triggers.

010-schematic.JPG

pins

011-pin.JPG

main.c

============

#include "project.h"

int main(void)

{

    CyGlobalIntEnable; /* Enable global interrupts. */

       

    Timer_Start() ;

   

    PWM_Start() ;

    for(;;)

    {

    }

}

============

Best Regards,

18-Feb-2020

Motoo Tanaka

Dear Motoo,

Thank you very much for your reply!

I am sorry for confusing you, that wasn't my purpose.

You were and still are right with Option (1). I want it to trigger and behave exactly like you have it in graphic (1).

Now for the timing:

     I need the PWM to be as accurate as possible. A loss in time in ns is not a problem. If it starts getting up in us, it is getting a problem. Therefor it would be interesting if the gate delay is under 1us.

As well as how I have to setup the IMO clock that it is as accurate as possible.

Thank you very much so far!

Kind Regards

Christoph 

0 Likes

Christoph,

From 50Hz requirement I get feeling that you looking for the frequency doubler for the AC mains. Is this so? What is going to happen with Figure 1 above when AC frequency changes?

/odissey1

0 Likes
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Dear Christoph-san,

IMHO, the delay of dff should be in the range of ns.

But I'm afraid that as datasheet states, the internal clock accuracy is +/-1% ~ +/-7%.

Even if we could divide clock to 20ms without any degradation, we still could see +/-200us ~ +/-1.4ms dispersion.

So for your application requirement an external crystal or clock of such accuracy is mandatory.

Best Regards,

21-Feb-2020

Motoo Tanaka

0 Likes