Problem with changing PSoC CPU clock

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
lock attach
Attachments are accessible only for community members.
Anonymous
Not applicable

Hi,

I'm having a difficult time with changing my PSoC's CPU clock (bus clock) to 72MHz.

I followed the instructions, but I still get this error: Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( CyBUS_CLK ).

I attached few screenshots so you can understand more easily the problem.

P.S.

I won't be able to upload the project.

0 Likes
1 Solution
lock attach
Attachments are accessible only for community members.

Thanks.

First, you seem to use an older version of PSoC Creator. I'm using 4.1, and have updated all components of your project to their current versions.

After, building, I get two timing warnings.

One is for FreeRunTimer, and is important. A 24.bit UDB timer can run with at most 28MHz according to the data sheet, but your using a 75MHz clock.

Second is for PWM_Out, and is because its reset signal comes from a control register, which in turn is clocked by MASTER_CLK. Setting the control registers to sync mode, and using a common 10kHz clock helps (the one which clocks the PWM itself).

Next the UARTa problems come up. I synced the clock lines to the same 10kHz clock, and the muxes too.

Remember: any signal coming from a control register is effectively in the MASTER_CLK domain. So it introduces signal at this frequency to all attached components (even via muxes, since you can e.g. switch the signal in the middle of a clock cycle)

The remaining problem is the rx_3 inout. Probably because its going through a mux it also needs to be synced to a slower clock. (Although setting the pin to 'transparent' helped).

View solution in original post

0 Likes
12 Replies