I would like to use a PSoCLP5 as a "power manager" for a large Xilinx FPGA. The PSoC5LP controls the sequencing of power supplies to the FPGA, monitors current and output voltage of every FPGA supply rail, temperature, etc.
All of these measurements are reported over I2C to the FPGA and via a USB to UART bridge (implemented in the PSoC5LP) to a host system. All of these requirements make the PSoC5LP a very good solution.
The PSoC5LP is powered continuously from a switching regulator that runs slightly above the dropout voltage of two LDOs. One of the LDOs produces +3.3V for most of the I/O and VDDA. VDDA is powered though a LC filter. The other LDO produces 1.8V for producing one of the I/O banks VDD.
Driving an unpowered FPGA will forward bias the ESD diodes on its inputs causing a voltage to appear on its power supply rails. Unless the generated voltage is kept below 2.5V when the FPGA is not powered, the Xilinx device may be damaged. One robust solution is to run the I/O between the PSoC5LP and the FPGA at 1.8V.
Here are a few questions:
1. Are there any power sequencing requirements among the PSOC5LP's power supply rails?
2. If an I/O bank is not in use is it safe to remove power for that bank? Will the rest of the PSoC5LP I/O on other banks continue to function normally?
Thanks for your help,
Wayne
