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Does anyone have any turnkey 8-bit parallel FIFO components?
My use case is:
- I wish to receive 8-bit data via DMA; I want a component where, every time I poke it via a signal, a parallel 8-bit bus is sampled and pushed onto a FIFO.
- I wish to send 8-bit data sourced via DMA; I want a component where, every time I poke it via a signal, it fetches an 8-bit value from a FIFO and expresses it on an 8-bit bus.
These used to exist on the old PSoC Sensei blog, but that's now gone. I know that you can't do this using the standard UDB tools and have to resort to low-level hacking via the datapath configuration tools; there are some extremely fuzzy instructions in https://www.cypress.com/documentation/application-notes/an82156-psoc-3-psoc-4-and-psoc-5lp-designing... but there's only about a page buried in an appendix. I'm really looking for some turnkey components I can just drop into my design.
(Plea to Cypress: please can we have these in the standard component library?)
Thanks!
Solved! Go to Solution.
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DaGi,
FIFO is needed for 10+MHz communication speed, you can use standard Control/Status registers for 1+MHz speed.
You can find a copy of the Brad Budlong's (AKA PSoC Sensei) 8/16-bit FIFOin component on this page, along with a demo project
Re: Difficulties using the parallel input bus (PI) in UDBs
You can find community FIFOout component on this page (I believe that it needs more testing)
Re: Is a FIFOout component available?
/odissey1
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DaGi,
FIFO is needed for 10+MHz communication speed, you can use standard Control/Status registers for 1+MHz speed.
You can find a copy of the Brad Budlong's (AKA PSoC Sensei) 8/16-bit FIFOin component on this page, along with a demo project
Re: Difficulties using the parallel input bus (PI) in UDBs
You can find community FIFOout component on this page (I believe that it needs more testing)
Re: Is a FIFOout component available?
/odissey1
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Belatedly: thanks!
I haven't tackled FIFOin, but I made FIFOout work; I did end up rewriting all the verilog to make it work the way I wanted (the consumer raises a req line to indicate it wants data, the FIFO raises a rdy line to indicate data is available, and then nothing happens until the consumer drops the req line again). You can find it here:
fluxengine/FluxEngine.cydsn/FIFOout at master · davidgiven/fluxengine · GitHub